| Message ID | 20190828030305.7190-2-qiangqing.zhang@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [V8,1/3] perf: imx8_ddr_perf: add AXI ID filter support | expand |
On Wed, Aug 28, 2019 at 03:05:39AM +0000, Joakim Zhang wrote: > Add i.MX8 ddr pmu user doc. > > ChangeLog: > V1 -> V4: > * new add in V4. > V4 -> V5: > * no change. > V5 -> V6: > * change the event name > V6 -> V7: > * no change. > V7 -> V8: > * improve the doc, add more details. > > Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> > --- > Documentation/admin-guide/perf/imx-ddr.rst | 51 ++++++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/admin-guide/perf/imx-ddr.rst > > diff --git a/Documentation/admin-guide/perf/imx-ddr.rst b/Documentation/admin-guide/perf/imx-ddr.rst > new file mode 100644 > index 000000000000..438de3be667b > --- /dev/null > +++ b/Documentation/admin-guide/perf/imx-ddr.rst > @@ -0,0 +1,51 @@ > +===================================================== > +Freescale i.MX8 DDR Performance Monitoring Unit (PMU) > +===================================================== > + > +There are no performance counters inside the DRAM controller, so performance > +signals are brought out to the edge of the controller where a set of 4 x 32 bit > +counters is implemented. This is controlled by the Performance log on parameter I don't understand what you mean by "Performance log on parameter". > +which causes a large number of PERF signals to be generated. > + > +Selection of the value for each counter is done via the config registiers. There registers > +is one register for each counter. Counter 0 is special in that it always counts > +“time” and when expired causes a lock on itself and the other counters and an > +interrupt ie enable of counter 0 is a global function. by "causes a lock on itself and the other counters" do you mean that Counter 0 counts down and, when it hits 0, all the counters stop counting? Will
> -----Original Message----- > From: Will Deacon <will@kernel.org> > Sent: 2019年8月28日 18:05 > To: Joakim Zhang <qiangqing.zhang@nxp.com> > Cc: mark.rutland@arm.com; robin.murphy@arm.com; Frank Li > <frank.li@nxp.com>; dl-linux-imx <linux-imx@nxp.com>; > linux-arm-kernel@lists.infradead.org > Subject: Re: [PATCH V8 2/3] Documentation: admin-guide: perf: add i.MX8 ddr > pmu user doc > > On Wed, Aug 28, 2019 at 03:05:39AM +0000, Joakim Zhang wrote: > > Add i.MX8 ddr pmu user doc. > > > > ChangeLog: > > V1 -> V4: > > * new add in V4. > > V4 -> V5: > > * no change. > > V5 -> V6: > > * change the event name > > V6 -> V7: > > * no change. > > V7 -> V8: > > * improve the doc, add more details. > > > > Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> > > --- > > Documentation/admin-guide/perf/imx-ddr.rst | 51 > > ++++++++++++++++++++++ > > 1 file changed, 51 insertions(+) > > create mode 100644 Documentation/admin-guide/perf/imx-ddr.rst > > > > diff --git a/Documentation/admin-guide/perf/imx-ddr.rst > > b/Documentation/admin-guide/perf/imx-ddr.rst > > new file mode 100644 > > index 000000000000..438de3be667b > > --- /dev/null > > +++ b/Documentation/admin-guide/perf/imx-ddr.rst > > @@ -0,0 +1,51 @@ > > +===================================================== > > +Freescale i.MX8 DDR Performance Monitoring Unit (PMU) > > +===================================================== > > + > > +There are no performance counters inside the DRAM controller, so > > +performance signals are brought out to the edge of the controller > > +where a set of 4 x 32 bit counters is implemented. This is controlled > > +by the Performance log on parameter > > I don't understand what you mean by "Performance log on parameter". [Joakim] From IC RM, it means Performance log on parameter field(event id)on counters control register. I will improve it. > > +which causes a large number of PERF signals to be generated. > > + > > +Selection of the value for each counter is done via the config > > +registiers. There > > registers [Joakim] Will Fix it. > > +is one register for each counter. Counter 0 is special in that it > > +always counts “time” and when expired causes a lock on itself and the > > +other counters and an interrupt ie enable of counter 0 is a global function. > > by "causes a lock on itself and the other counters" do you mean that Counter > 0 counts down and, when it hits 0, all the counters stop counting? [Joakim] Yes, as it commented in ddr_perf_irq_handler(): /* * When the cycle counter overflows, all counters are stopped, * and an IRQ is raised. If any other counter overflows, it * continues counting, and no IRQ is raised. * * Cycles occur at least 4 times as often as other events, so we * can update all events on a cycle counter overflow and not * lose events. */ Best Regards, Joakim Zhang > Will
diff --git a/Documentation/admin-guide/perf/imx-ddr.rst b/Documentation/admin-guide/perf/imx-ddr.rst new file mode 100644 index 000000000000..438de3be667b --- /dev/null +++ b/Documentation/admin-guide/perf/imx-ddr.rst @@ -0,0 +1,51 @@ +===================================================== +Freescale i.MX8 DDR Performance Monitoring Unit (PMU) +===================================================== + +There are no performance counters inside the DRAM controller, so performance +signals are brought out to the edge of the controller where a set of 4 x 32 bit +counters is implemented. This is controlled by the Performance log on parameter +which causes a large number of PERF signals to be generated. + +Selection of the value for each counter is done via the config registiers. There +is one register for each counter. Counter 0 is special in that it always counts +“time” and when expired causes a lock on itself and the other counters and an +interrupt ie enable of counter 0 is a global function. + +The "format" directory describes format of the config (event ID) and config1 +(AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/ +devices/imx8_ddr0/format/. The "events" directory describes the events types +hardware supported that can be used with perf tool, see /sys/bus/event_source/ +devices/imx8_ddr0/events/. + e.g.:: + perf stat -a -e imx8_ddr0/cycles/ cmd + perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd + +AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write) +to count reading or writing matches filter setting. Filter setting is various +from different DRAM controller implementations, which is distinguished by quirks +in the driver. + +* With DDR_CAP_AXI_ID_FILTER quirk. + Filter is defined with two configuration parts: + --AXI_ID defines AxID matching value. + --AXI_MASKING defines which bits of AxID are meaningful for the matching. + 0：corresponding bit is masked. + 1: corresponding bit is not masked, i.e. used to do the matching. + + AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter. + When non-masked bits are matching corresponding AXI_ID bits then counter is + incremented. Perf counter is incremented if + AxID && AXI_MASKING == AXI_ID && AXI_MASKING + + This filter doesn't support filter different AXI ID for axid-read and axid-write + event at the same time as this filter is shared between counters. + e.g.:: + perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd + perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd + + NOTE: axi_mask is inverted in userspace(i.e. set bits are bits to mask), and + it will be reverted in driver automatically. so that the user can just specify + axi_id to monitor a specific id, rather than having to specify axi_mask. + e.g.:: + perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12
Add i.MX8 ddr pmu user doc. ChangeLog: V1 -> V4: * new add in V4. V4 -> V5: * no change. V5 -> V6: * change the event name V6 -> V7: * no change. V7 -> V8: * improve the doc, add more details. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> --- Documentation/admin-guide/perf/imx-ddr.rst | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/admin-guide/perf/imx-ddr.rst