| Message ID | 20190828135218.7307-2-linus.walleij@linaro.org (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | b786a05f6ce4ff29ff9ef438c6111f339672f88d |
| Headers | show |
| Series | [1/2] ARM: dts: ux500: Fix up the thermal nodes | expand |
On 28/08/2019 15:52, Linus Walleij wrote: > After moving the DB8500 thermal driver to use device tree > we define the default thermal zone for the Ux500 in the > device tree replacing the oldstyle hardcoded trigger > points. > > This default thermal zone utilizes the cpufreq driver > (using the generic OF cpufreq back-end) as a passive > cooling device, and defines a critical trip point when > the temperature goes above 85 degrees celsius which will > (hopefully) make the system shut down if the temperature > cannot be controlled. > > This default policy can later be augmented for specific > subdevices if these have tighter temperature conditions. > > After this patch we get: > > /sys/class/thermal/thermal_zone0 (CPU thermal zone) > This reports the rough temperature and trip points > from the thermal zone in the device tree. > > By executing two yes > /dev/null & jobs fully utilizing > the two CPU cores we can notice the temperature climbing > in the thermal zone in response and falling when we kill > the jobs. > > /syc/class/thermal/cooling_device0 (cpufreq cooling) > this reports all 4 available cpufreq frequencies as > states. > > Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org> > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > arch/arm/boot/dts/ste-dbx5x0.dtsi | 57 +++++++++++++++++++------------ > 1 file changed, 36 insertions(+), 21 deletions(-) > > diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi > index 7953eea7c486..9ee50f339e7a 100644 > --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi > +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi > @@ -44,6 +44,7 @@ > clocks = <&prcmu_clk PRCMU_ARMSS>; > clock-names = "cpu"; > clock-latency = <20000>; > + #cooling-cells = <2>; > }; > CPU1: cpu@301 { > device_type = "cpu"; > @@ -52,6 +53,39 @@ > }; > }; > > + thermal-zones { > + /* > + * Thermal zone for the SoC, using the thermal sensor in the > + * PRCMU for temperature and the cpufreq driver for passive > + * cooling. > + */ > + cpu_thermal: cpu-thermal { > + polling-delay-passive = <0>; > + polling-delay = <1000>; Assuming zero for both. If the temperature is below 'cpu_alert', no polling will be done (which good for PM reason). When the temperature is reached, then the sensor will fire an interrupt, leading to the thermal zone update, which in turn does the mitigation. As the temperature is updated by the interrupts, a polling is pointless when mitigating because the tz is updated automatically. On the other hand, I don't know if the slope of the temperature change will be correctly represented with this change and how that may impact the governor if the temperature sampling is variable (not based on polling but on interrupt events). IMO the polling-delay should be zero, and the polling-delay-passive should be something like 250. In order to disable the mitigation, the sensor should update the temperature with a value under the 'cpu_alert'. I guess that is the case because the lowest temperature is 15000mC, right ? > + thermal-sensors = <&thermal>; > + > + trips { > + cpu_alert: cpu-alert { > + temperature = <70000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + cpu-crit { > + temperature = <85000>; > + hysteresis = <0>; > + type = "critical"; > + }; > + }; > + > + cooling-maps { > + trip = <&cpu_alert>; > + cooling-device = <&CPU0 0 2>; Except it is done on purpose, 0 2 means restricting the number of state of the cooling device. It could/should be: <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + contribution = <100>; > + }; > + }; > + }; > + > soc { > #address-cells = <1>; > #size-cells = <1>; > @@ -502,33 +536,14 @@ > reg = <0x80157450 0xC>; > }; > > - thermal@801573c0 { > + thermal: thermal@801573c0 { > compatible = "stericsson,db8500-thermal"; > reg = <0x801573c0 0x40>; > interrupt-parent = <&prcmu>; > interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, > <22 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; > - num-trips = <4>; > - > - trip0-temp = <70000>; > - trip0-type = "active"; > - trip0-cdev-num = <1>; > - trip0-cdev-name0 = "thermal-cpufreq-0"; > - > - trip1-temp = <75000>; > - trip1-type = "active"; > - trip1-cdev-num = <1>; > - trip1-cdev-name0 = "thermal-cpufreq-0"; > - > - trip2-temp = <80000>; > - trip2-type = "active"; > - trip2-cdev-num = <1>; > - trip2-cdev-name0 = "thermal-cpufreq-0"; > - > - trip3-temp = <85000>; > - trip3-type = "critical"; > - trip3-cdev-num = <0>; > + #thermal-sensor-cells = <0>; > }; > > db8500-prcmu-regulators { >
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 7953eea7c486..9ee50f339e7a 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -44,6 +44,7 @@ clocks = <&prcmu_clk PRCMU_ARMSS>; clock-names = "cpu"; clock-latency = <20000>; + #cooling-cells = <2>; }; CPU1: cpu@301 { device_type = "cpu"; @@ -52,6 +53,39 @@ }; }; + thermal-zones { + /* + * Thermal zone for the SoC, using the thermal sensor in the + * PRCMU for temperature and the cpufreq driver for passive + * cooling. + */ + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + + thermal-sensors = <&thermal>; + + trips { + cpu_alert: cpu-alert { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu-crit { + temperature = <85000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + trip = <&cpu_alert>; + cooling-device = <&CPU0 0 2>; + contribution = <100>; + }; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -502,33 +536,14 @@ reg = <0x80157450 0xC>; }; - thermal@801573c0 { + thermal: thermal@801573c0 { compatible = "stericsson,db8500-thermal"; reg = <0x801573c0 0x40>; interrupt-parent = <&prcmu>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, <22 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; - num-trips = <4>; - - trip0-temp = <70000>; - trip0-type = "active"; - trip0-cdev-num = <1>; - trip0-cdev-name0 = "thermal-cpufreq-0"; - - trip1-temp = <75000>; - trip1-type = "active"; - trip1-cdev-num = <1>; - trip1-cdev-name0 = "thermal-cpufreq-0"; - - trip2-temp = <80000>; - trip2-type = "active"; - trip2-cdev-num = <1>; - trip2-cdev-name0 = "thermal-cpufreq-0"; - - trip3-temp = <85000>; - trip3-type = "critical"; - trip3-cdev-num = <0>; + #thermal-sensor-cells = <0>; }; db8500-prcmu-regulators {
After moving the DB8500 thermal driver to use device tree we define the default thermal zone for the Ux500 in the device tree replacing the oldstyle hardcoded trigger points. This default thermal zone utilizes the cpufreq driver (using the generic OF cpufreq back-end) as a passive cooling device, and defines a critical trip point when the temperature goes above 85 degrees celsius which will (hopefully) make the system shut down if the temperature cannot be controlled. This default policy can later be augmented for specific subdevices if these have tighter temperature conditions. After this patch we get: /sys/class/thermal/thermal_zone0 (CPU thermal zone) This reports the rough temperature and trip points from the thermal zone in the device tree. By executing two yes > /dev/null & jobs fully utilizing the two CPU cores we can notice the temperature climbing in the thermal zone in response and falling when we kill the jobs. /syc/class/thermal/cooling_device0 (cpufreq cooling) this reports all 4 available cpufreq frequencies as states. Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 57 +++++++++++++++++++------------ 1 file changed, 36 insertions(+), 21 deletions(-)