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[73.37.219.234]) by smtp.gmail.com with ESMTPSA id i10sm2291519ioq.51.2019.08.28.08.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 08:01:14 -0700 (PDT) From: Adam Ford To: linux-omap@vger.kernel.org Subject: [RFC] ARM: omap3: Enable HWMODS for HW Random Number Generator Date: Wed, 28 Aug 2019 10:00:37 -0500 Message-Id: <20190828150037.2640-1-aford173@gmail.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190828_080122_601939_CB559BE9 X-CRM114-Status: GOOD ( 15.35 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (aford173[at]gmail.com) 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (aford173[at]gmail.com) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:d41 listed in] [list.dnswl.org] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Paul Walmsley , aaro.koskinen@iki.fi, Tony Lindgren , adam.ford@logicpd.com, Russell King , linux-kernel@vger.kernel.org, t-kristo@ti.com, Rob Herring , =?utf-8?q?Beno=C3=AEt_Co?= =?utf-8?q?usson?= , pali.rohar@gmail.com, Adam Ford , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The datasheet for the AM3517 shows the RNG is connected to L4. It shows the module address for the RNG is 0x480A0000, and it matches the omap2.dtsi description. Since the driver can support omap2 and omap4, it seems reasonable to assume the omap3 would use the same core for the RNG. This RFC, mimics much of the omap2 hwmods on the OMAP3. It also adds the necessary clock for driving the RNG. Unfortunately, it appears non-functional. If anyone has any suggestions on how to finish the hwmod (or port it to the newer l4 device tree format), feedback is requested. Currently the hwmods repond as follows: [ 0.245697] omap_hwmod: rng: _wait_target_ready failed: -22 [ 0.245727] omap_hwmod: rng: cannot be enabled for reset (3) [ 6.780792] omap_hwmod: rng: _wait_target_ready failed: -22 Signed-off-by: Adam Ford diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index 945537aee3ca..05891dff7fa1 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -189,7 +189,7 @@ <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&rng_ick>, <&ssi_ick>; }; }; diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 037529a9e969..82330a66e35c 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -17,6 +17,7 @@ #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) #define OMAP3430_ST_AES2_SHIFT 28 +#define OMAP34XX_ST_RNG_SHIFT 2 #define OMAP3430_ST_SHA12_SHIFT 27 #define AM35XX_ST_UART4_SHIFT 23 #define OMAP3430_ST_HDQ_SHIFT 22 diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index f52438bdfc14..bae4487383b6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1627,6 +1627,42 @@ static struct omap_hwmod omap3xxx_gpmc_hwmod = { .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS, }; +/* RNG */ + +static struct omap_hwmod_class_sysconfig omap3_rng_sysc = { + .rev_offs = 0x3c, + .sysc_offs = 0x40, + .syss_offs = 0x44, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3_rng_hwmod_class = { + .name = "rng", + .sysc = &omap3_rng_sysc, +}; + +struct omap_hwmod omap3xxx_rng_hwmod = { + .name = "rng", + .main_clk = "rng_ick", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .idlest_reg_id = 4, + .idlest_idle_bit = OMAP34XX_ST_RNG_SHIFT, + }, + }, + /* + * XXX The first read from the SYSSTATUS register of the RNG + * after the SYSCONFIG SOFTRESET bit is set triggers an + * imprecise external abort. It's unclear why this happens. + * Until this is analyzed, skip the IP block reset. + */ + .flags = HWMOD_INIT_NO_RESET, + .class = &omap3_rng_hwmod_class, +}; + /* * interfaces */ @@ -2508,6 +2544,13 @@ static struct omap_hwmod omap3xxx_sham_hwmod = { .class = &omap3xxx_sham_class, }; +/* l4_core -> rng */ +struct omap_hwmod_ocp_if omap3xxx_l4_core__rng = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_rng_hwmod, + .clk = "rng_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { .master = &omap3xxx_l4_core_hwmod, @@ -2769,6 +2812,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l4_core__mmu_isp, &omap3xxx_l3_main__mmu_iva, &omap3xxx_l4_core__ssi, + &omap3xxx_l4_core__rng, NULL, }; @@ -2788,6 +2832,7 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { &am35xx_l4_core__mdio, &am35xx_emac__l3, &am35xx_l4_core__emac, + &omap3xxx_l4_core__rng, NULL, };