| Message ID | 20190903033132.17661-1-andy.tang@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: lx2160a: add tmu device node | expand |
On Tue, Sep 03, 2019 at 11:31:32AM +0800, Yuantian Tang wrote: > Add the TMU (Thermal Monitoring Unit) device node to enable > TMU feature. > > Signed-off-by: Yuantian Tang <andy.tang@nxp.com> > --- > .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 108 +++++++++++++++--- > 1 file changed, 92 insertions(+), 16 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > index 39d497df769e..e70ddd01cd84 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > @@ -6,6 +6,7 @@ > > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/thermal/thermal.h> > > /memreserve/ 0x80000000 0x00010000; > > @@ -24,7 +25,7 @@ > #size-cells = <0>; > > // 8 clusters having 2 Cortex-A72 cores each > - cpu@0 { > + cpu0: cpu@0 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -38,9 +39,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster0_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@1 { > + cpu1: cpu@1 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -54,9 +56,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster0_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@100 { > + cpu100: cpu@100 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -70,9 +73,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster1_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@101 { > + cpu101: cpu@101 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -86,9 +90,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster1_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@200 { > + cpu200: cpu@200 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -102,9 +107,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster2_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@201 { > + cpu201: cpu@201 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -118,9 +124,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster2_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@300 { > + cpu300: cpu@300 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -134,9 +141,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster3_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@301 { > + cpu301: cpu@301 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -150,9 +158,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster3_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@400 { > + cpu400: cpu@400 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -166,9 +175,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster4_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@401 { > + cpu401: cpu@401 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -182,9 +192,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster4_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@500 { > + cpu500: cpu@500 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -198,9 +209,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster5_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@501 { > + cpu501: cpu@501 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -214,9 +226,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster5_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@600 { > + cpu600: cpu@600 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -230,9 +243,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster6_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@601 { > + cpu601: cpu@601 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -246,9 +260,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster6_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@700 { > + cpu700: cpu@700 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -262,9 +277,10 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster7_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > - cpu@701 { > + cpu701: cpu@701 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > enable-method = "psci"; > @@ -278,6 +294,7 @@ > i-cache-sets = <192>; > next-level-cache = <&cluster7_l2>; > cpu-idle-states = <&cpu_pw20>; > + #cooling-cells = <2>; > }; > > cluster0_l2: l2-cache0 { > @@ -422,6 +439,51 @@ > clock-output-names = "sysclk"; > }; > > + thermal-zones { > + core_thermal1: core-thermal1 { > + polling-delay-passive = <1000>; > + polling-delay = <5000>; > + thermal-sensors = <&tmu 0>; > + > + trips { > + core_cluster_alert: core-cluster-alert { > + temperature = <85000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + core_cluster_crit: core-cluster-crit { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + > + cooling-maps { > + map0 { > + trip = <&core_cluster_alert>; > + cooling-device = > + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + }; > + }; > + > soc { > compatible = "simple-bus"; > #address-cells = <2>; > @@ -689,6 +751,20 @@ > status = "disabled"; > }; > > + tmu: tmu@1f80000 { Keep the nodes sorted in unit-address. > + compatible = "fsl,qoriq-tmu"; > + reg = <0x0 0x1f80000 0x0 0x10000>; > + interrupts = <0 23 0x4>; IRQ_TYPE_LEVEL_HIGH > + fsl,tmu-range = <0x800000E6 0x8001017D>; Use lowercase for hex values. Shawn > + fsl,tmu-calibration = > + /* Calibration data group 1 */ > + <0x00000000 0x00000035 > + /* Calibration data group 2 */ > + 0x00010001 0x00000154>; > + little-endian; > + #thermal-sensor-cells = <1>; > + }; > + > uart0: serial@21c0000 { > compatible = "arm,sbsa-uart","arm,pl011"; > reg = <0x0 0x21c0000 0x0 0x1000>; > -- > 2.17.1 >
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 39d497df769e..e70ddd01cd84 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> /memreserve/ 0x80000000 0x00010000; @@ -24,7 +25,7 @@ #size-cells = <0>; // 8 clusters having 2 Cortex-A72 cores each - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -38,9 +39,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster0_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -54,9 +56,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster0_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@100 { + cpu100: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -70,9 +73,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster1_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@101 { + cpu101: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -86,9 +90,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster1_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@200 { + cpu200: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -102,9 +107,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster2_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@201 { + cpu201: cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -118,9 +124,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster2_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@300 { + cpu300: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -134,9 +141,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster3_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@301 { + cpu301: cpu@301 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -150,9 +158,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster3_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@400 { + cpu400: cpu@400 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -166,9 +175,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster4_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@401 { + cpu401: cpu@401 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -182,9 +192,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster4_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@500 { + cpu500: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -198,9 +209,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster5_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@501 { + cpu501: cpu@501 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -214,9 +226,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster5_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@600 { + cpu600: cpu@600 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -230,9 +243,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster6_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@601 { + cpu601: cpu@601 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -246,9 +260,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster6_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@700 { + cpu700: cpu@700 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -262,9 +277,10 @@ i-cache-sets = <192>; next-level-cache = <&cluster7_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; - cpu@701 { + cpu701: cpu@701 { device_type = "cpu"; compatible = "arm,cortex-a72"; enable-method = "psci"; @@ -278,6 +294,7 @@ i-cache-sets = <192>; next-level-cache = <&cluster7_l2>; cpu-idle-states = <&cpu_pw20>; + #cooling-cells = <2>; }; cluster0_l2: l2-cache0 { @@ -422,6 +439,51 @@ clock-output-names = "sysclk"; }; + thermal-zones { + core_thermal1: core-thermal1 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 0>; + + trips { + core_cluster_alert: core-cluster-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core_cluster_crit: core-cluster-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -689,6 +751,20 @@ status = "disabled"; }; + tmu: tmu@1f80000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f80000 0x0 0x10000>; + interrupts = <0 23 0x4>; + fsl,tmu-range = <0x800000E6 0x8001017D>; + fsl,tmu-calibration = + /* Calibration data group 1 */ + <0x00000000 0x00000035 + /* Calibration data group 2 */ + 0x00010001 0x00000154>; + little-endian; + #thermal-sensor-cells = <1>; + }; + uart0: serial@21c0000 { compatible = "arm,sbsa-uart","arm,pl011"; reg = <0x0 0x21c0000 0x0 0x1000>;
Add the TMU (Thermal Monitoring Unit) device node to enable TMU feature. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> --- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 108 +++++++++++++++--- 1 file changed, 92 insertions(+), 16 deletions(-)