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Fri, 6 Sep 2019 05:36:04 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 6 Sep 2019 05:36:02 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 6 Sep 2019 05:36:02 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x86AZxp9060862; Fri, 6 Sep 2019 05:36:00 -0500 From: Tero Kristo To: , , , , , Subject: [PATCHv4 01/10] dt-bindings: omap: add new binding for PRM instances Date: Fri, 6 Sep 2019 13:35:58 +0300 Message-ID: <20190906103558.17694-1-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830121816.30034-2-t-kristo@ti.com> References: <20190830121816.30034-2-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190906_033612_563428_643474F4 X-CRM114-Status: GOOD ( 11.56 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [198.47.19.141 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add new binding for OMAP PRM (Power and Reset Manager) instances. Each of these will act as a power domain controller and potentially as a reset provider. Signed-off-by: Tero Kristo Reviewed-by: Rob Herring Reviewed-by: Tony Lindgren --- v4: - renamed nodes as power-controller - added documentation about hierarchy .../devicetree/bindings/arm/omap/prm-inst.txt | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/omap/prm-inst.txt diff --git a/Documentation/devicetree/bindings/arm/omap/prm-inst.txt b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt new file mode 100644 index 000000000000..7c7527c37734 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt @@ -0,0 +1,35 @@ +OMAP PRM instance bindings + +Power and Reset Manager is an IP block on OMAP family of devices which +handle the power domains and their current state, and provide reset +handling for the domains and/or separate IP blocks under the power domain +hierarchy. A PRM instance node must be a child of a PRM node [1]. + +[1] Documentation/devicetree/bindings/arm/omap/prcm.txt + +Required properties: +- compatible: Must be one of: + "ti,am3-prm-inst" + "ti,am4-prm-inst" + "ti,omap4-prm-inst" + "ti,omap5-prm-inst" + "ti,dra7-prm-inst" +- reg: Contains PRM instance register address range + (base address and length) + +Optional properties: +- #reset-cells: Should be 1 if the PRM instance in question supports resets. +- clocks: Associated clocks for the reset signals if any. Certain reset + signals can't be toggled properly without functional clock + being active for them. + +Example: + +&prm { + prm_dsp2: power-controller@1b00 { + compatible = "ti,dra7-prm-inst"; + reg = <0x1b00 0x40>; + #reset-cells = <1>; + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; + }; +};