| Message ID | 20190912175132.411-2-jernej.skrabec@siol.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | media: Introduce Allwinner H3 deinterlace driver | expand |
diff --git a/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt b/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt index 1464a4713553..2005bb486705 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt +++ b/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt @@ -8,6 +8,7 @@ bus. Required properties: - compatible: Must be one of: - allwinner,sun5i-a13-mbus + - allwinner,sun8i-h3-mbus - reg: Offset and length of the register set for the controller - clocks: phandle to the clock driving the controller - dma-ranges: See section 2.3.9 of the DeviceTree Specification
Allwinner H3 SoC also contains MBUS controller. Add compatible for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> --- Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt | 1 + 1 file changed, 1 insertion(+)