| Message ID | 20190916125022.10754-6-narmstrong@baylibre.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 934de3415e5e63561530d1c571dc47e116a9c63a |
| Headers | show |
| Series | arm64: dts: meson-g12: add support for PCIe | expand |
On Mon, Sep 16, 2019 at 02:50:21PM +0200, Neil Armstrong wrote: > This adds the Amlogic G12A PCI Express controller node, also > using the USB3+PCIe Combo PHY. > > The PHY mode selection is static, thus the USB3+PCIe Combo PHY > phandle would need to be removed from the USB control node if the > shared differential lines are used for PCIe instead of USB3. > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> > --- > .../boot/dts/amlogic/meson-g12-common.dtsi | 33 +++++++++++++++++++ > arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 4 +++ > 2 files changed, 37 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi > index 852cf9cf121b..7330dc37b7a6 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi > @@ -95,6 +95,39 @@ > #size-cells = <2>; > ranges; > > + pcie: pcie@fc000000 { > + compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; > + reg = <0x0 0xfc000000 0x0 0x400000 > + 0x0 0xff648000 0x0 0x2000 > + 0x0 0xfc400000 0x0 0x200000>; > + reg-names = "elbi", "cfg", "config"; > + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; > + bus-range = <0x0 0xff>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000 > + 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; > + > + clocks = <&clkc CLKID_PCIE_PHY > + &clkc CLKID_PCIE_COMB > + &clkc CLKID_PCIE_PLL>; > + clock-names = "general", > + "pclk", > + "port"; > + resets = <&reset RESET_PCIE_CTRL_A>, > + <&reset RESET_PCIE_APB>; > + reset-names = "port", > + "apb"; > + num-lanes = <1>; > + phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; > + phy-names = "pcie"; > + status = "disabled"; > + }; > + > ethmac: ethernet@ff3f0000 { > compatible = "amlogic,meson-axg-dwmac", > "snps,dwmac-3.70a", > diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi > index 91492819d0d8..ee9ea3c69433 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi > @@ -135,6 +135,10 @@ > power-domains = <&pwrc PWRC_SM1_ETH_ID>; > }; > > +&pcie { > + power-domains = <&pwrc PWRC_SM1_PCIE_ID>; > +}; > + > &pwrc { > compatible = "amlogic,meson-sm1-pwrc"; > }; > -- > 2.22.0 >
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 852cf9cf121b..7330dc37b7a6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -95,6 +95,39 @@ #size-cells = <2>; ranges; + pcie: pcie@fc000000 { + compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; + reg = <0x0 0xfc000000 0x0 0x400000 + 0x0 0xff648000 0x0 0x2000 + 0x0 0xfc400000 0x0 0x200000>; + reg-names = "elbi", "cfg", "config"; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000 + 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; + + clocks = <&clkc CLKID_PCIE_PHY + &clkc CLKID_PCIE_COMB + &clkc CLKID_PCIE_PLL>; + clock-names = "general", + "pclk", + "port"; + resets = <&reset RESET_PCIE_CTRL_A>, + <&reset RESET_PCIE_APB>; + reset-names = "port", + "apb"; + num-lanes = <1>; + phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; + phy-names = "pcie"; + status = "disabled"; + }; + ethmac: ethernet@ff3f0000 { compatible = "amlogic,meson-axg-dwmac", "snps,dwmac-3.70a", diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 91492819d0d8..ee9ea3c69433 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -135,6 +135,10 @@ power-domains = <&pwrc PWRC_SM1_ETH_ID>; }; +&pcie { + power-domains = <&pwrc PWRC_SM1_PCIE_ID>; +}; + &pwrc { compatible = "amlogic,meson-sm1-pwrc"; };
This adds the Amlogic G12A PCI Express controller node, also using the USB3+PCIe Combo PHY. The PHY mode selection is static, thus the USB3+PCIe Combo PHY phandle would need to be removed from the USB control node if the shared differential lines are used for PCIe instead of USB3. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- .../boot/dts/amlogic/meson-g12-common.dtsi | 33 +++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 4 +++ 2 files changed, 37 insertions(+)