| Message ID | 20190924074533.6618-4-tudor.ambarus@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mtd: spi-nor: Quad Enable and (un)lock methods | expand |
On Tue, 24 Sep 2019 07:45:58 +0000 <Tudor.Ambarus@microchip.com> wrote: > From: Tudor Ambarus <tudor.ambarus@microchip.com> > > n_tx was never used, drop it. Replace 'const u8 *txbuf' with 'u8 opcode', > to comply with the SPI NOR int (*read_reg)() method. The 'const' > qualifier has no meaning for parameters passed by value, drop it. > Going furher, the opcode was passed to cqspi_calc_rdreg() and never used, > drop it. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> > --- > drivers/mtd/spi-nor/cadence-quadspi.c | 15 +++++++-------- > 1 file changed, 7 insertions(+), 8 deletions(-) > > diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c > index ebda612641a4..22008fecd326 100644 > --- a/drivers/mtd/spi-nor/cadence-quadspi.c > +++ b/drivers/mtd/spi-nor/cadence-quadspi.c > @@ -285,7 +285,7 @@ static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) > return IRQ_HANDLED; > } > > -static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode) > +static unsigned int cqspi_calc_rdreg(struct spi_nor *nor) > { > struct cqspi_flash_pdata *f_pdata = nor->priv; > u32 rdreg = 0; > @@ -354,8 +354,7 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) > return cqspi_wait_idle(cqspi); > } > > -static int cqspi_command_read(struct spi_nor *nor, > - const u8 *txbuf, const unsigned n_tx, > +static int cqspi_command_read(struct spi_nor *nor, u8 opcode, > u8 *rxbuf, size_t n_rx) > { > struct cqspi_flash_pdata *f_pdata = nor->priv; > @@ -373,9 +372,9 @@ static int cqspi_command_read(struct spi_nor *nor, > return -EINVAL; > } > > - reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; > + reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; > > - rdreg = cqspi_calc_rdreg(nor, txbuf[0]); > + rdreg = cqspi_calc_rdreg(nor); > writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); > > reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); > @@ -471,7 +470,7 @@ static int cqspi_read_setup(struct spi_nor *nor) > unsigned int reg; > > reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; > - reg |= cqspi_calc_rdreg(nor, nor->read_opcode); > + reg |= cqspi_calc_rdreg(nor); > > /* Setup dummy clock cycles */ > dummy_clk = nor->read_dummy; > @@ -604,7 +603,7 @@ static int cqspi_write_setup(struct spi_nor *nor) > /* Set opcode. */ > reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; > writel(reg, reg_base + CQSPI_REG_WR_INSTR); > - reg = cqspi_calc_rdreg(nor, nor->program_opcode); > + reg = cqspi_calc_rdreg(nor); > writel(reg, reg_base + CQSPI_REG_RD_INSTR); > > reg = readl(reg_base + CQSPI_REG_SIZE); > @@ -1087,7 +1086,7 @@ static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len) > > ret = cqspi_set_protocol(nor, 0); > if (!ret) > - ret = cqspi_command_read(nor, &opcode, 1, buf, len); > + ret = cqspi_command_read(nor, opcode, buf, len); > > return ret; > }
On 09/24/2019 10:45 AM, Tudor Ambarus - M18064 wrote: > From: Tudor Ambarus <tudor.ambarus@microchip.com> > > n_tx was never used, drop it. Replace 'const u8 *txbuf' with 'u8 opcode', > to comply with the SPI NOR int (*read_reg)() method. The 'const' > qualifier has no meaning for parameters passed by value, drop it. > Going furher, the opcode was passed to cqspi_calc_rdreg() and never used, > drop it. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> > --- > drivers/mtd/spi-nor/cadence-quadspi.c | 15 +++++++-------- > 1 file changed, 7 insertions(+), 8 deletions(-) Applied to spi-nor/next.
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index ebda612641a4..22008fecd326 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -285,7 +285,7 @@ static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) return IRQ_HANDLED; } -static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode) +static unsigned int cqspi_calc_rdreg(struct spi_nor *nor) { struct cqspi_flash_pdata *f_pdata = nor->priv; u32 rdreg = 0; @@ -354,8 +354,7 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) return cqspi_wait_idle(cqspi); } -static int cqspi_command_read(struct spi_nor *nor, - const u8 *txbuf, const unsigned n_tx, +static int cqspi_command_read(struct spi_nor *nor, u8 opcode, u8 *rxbuf, size_t n_rx) { struct cqspi_flash_pdata *f_pdata = nor->priv; @@ -373,9 +372,9 @@ static int cqspi_command_read(struct spi_nor *nor, return -EINVAL; } - reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; + reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; - rdreg = cqspi_calc_rdreg(nor, txbuf[0]); + rdreg = cqspi_calc_rdreg(nor); writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); @@ -471,7 +470,7 @@ static int cqspi_read_setup(struct spi_nor *nor) unsigned int reg; reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; - reg |= cqspi_calc_rdreg(nor, nor->read_opcode); + reg |= cqspi_calc_rdreg(nor); /* Setup dummy clock cycles */ dummy_clk = nor->read_dummy; @@ -604,7 +603,7 @@ static int cqspi_write_setup(struct spi_nor *nor) /* Set opcode. */ reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; writel(reg, reg_base + CQSPI_REG_WR_INSTR); - reg = cqspi_calc_rdreg(nor, nor->program_opcode); + reg = cqspi_calc_rdreg(nor); writel(reg, reg_base + CQSPI_REG_RD_INSTR); reg = readl(reg_base + CQSPI_REG_SIZE); @@ -1087,7 +1086,7 @@ static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len) ret = cqspi_set_protocol(nor, 0); if (!ret) - ret = cqspi_command_read(nor, &opcode, 1, buf, len); + ret = cqspi_command_read(nor, opcode, buf, len); return ret; }