diff mbox series

[1/3] ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg

Message ID 20190926232820.27676-2-chris.packham@alliedtelesis.co.nz (mailing list archive)
State Mainlined
Commit da29334c751187b0bb89bdfa6c0302697848fa1a
Headers show
Series ARM: dts: SDRAM and L2 cache EDAC for Armada SoCs | expand

Commit Message

Chris Packham Sept. 26, 2019, 11:28 p.m. UTC 
Enable L2 cache parity and ECC on the db-xc3-24g4xg board so that cache
operations are protected and errors can be flagged to the EDAC
subsystem.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
 arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++
 1 file changed, 5 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
index df048050615f..4ec0ae01b61d 100644
--- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
+++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
@@ -33,6 +33,11 @@ 
 	};
 };
 
+&L2 {
+	arm,parity-enable;
+	marvell,ecc-enable;
+};
+
 &devbus_bootcs {
 	status = "okay";