From patchwork Fri Oct 4 11:59:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 11174323 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5F4C613BD for ; Fri, 4 Oct 2019 12:06:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3966A21D71 for ; Fri, 4 Oct 2019 12:06:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="COBMifV7" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3966A21D71 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kaod.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DtTWTBnqs/TceYkYmAhsmj+IAPAsjp6/f4ca3oA3Sj0=; b=COBMifV7XGi0QN 8mnZHPsWFO0Ixm8Ozy/96w/icJw3TYzDE+PovndJWYJ7abA0mrvSPYHpUzmtYbHRNr3fiFDB/lEXy C4x11/jgVaVEm8o866FNE9iCRuPcPWYD5/zdp4jhPVOilgKchlEGf7/dmnO9oDWcHt38ueaQdZdIJ stD5lZ49dy/uIgIySckTaLNA0sqPG9TUcb1GXD5TVI6tMXHD6j9G20utNxWXB9Es0TA1QyNIAbYza 92RlWUspwsNp2Wu1NcD6JtzwyJhIOrdexRwy3lPppTrQKbL68GPdAMGCgZd40qDs0ClPMAAlnZ+Nz Vc+mEzhnmfb6Z92yMC8g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iGMLd-00045x-1m; Fri, 04 Oct 2019 12:06:13 +0000 Received: from 3.mo2.mail-out.ovh.net ([46.105.58.226]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iGMI7-0008Ip-Dn for linux-arm-kernel@lists.infradead.org; Fri, 04 Oct 2019 12:02:38 +0000 Received: from player792.ha.ovh.net (unknown [10.109.159.203]) by mo2.mail-out.ovh.net (Postfix) with ESMTP id AE08C1AEF26 for ; Fri, 4 Oct 2019 14:02:32 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player792.ha.ovh.net (Postfix) with ESMTPSA id D0B19AA66169; Fri, 4 Oct 2019 12:02:15 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: linux-mtd@lists.infradead.org, Tudor Ambarus Subject: [PATCH 10/16] mtd: spi-nor: aspeed: Introduce segment operations Date: Fri, 4 Oct 2019 13:59:13 +0200 Message-Id: <20191004115919.20788-11-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191004115919.20788-1-clg@kaod.org> References: <20191004115919.20788-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 3807793485289262003 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrhedugdegtdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191004_050235_938036_C9543B50 X-CRM114-Status: GOOD ( 18.09 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [46.105.58.226 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Vignesh Raghavendra , linux-aspeed@lists.ozlabs.org, Andrew Jeffery , Richard Weinberger , Marek Vasut , Joel Stanley , Miquel Raynal , Brian Norris , David Woodhouse , linux-arm-kernel@lists.infradead.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org AST2600 will use a different encoding for the addresses defined in the Segment Register. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery --- drivers/mtd/spi-nor/aspeed-smc.c | 78 ++++++++++++++++++++++++-------- 1 file changed, 58 insertions(+), 20 deletions(-) diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c index c5a0c8d94371..7cdd84a2ca82 100644 --- a/drivers/mtd/spi-nor/aspeed-smc.c +++ b/drivers/mtd/spi-nor/aspeed-smc.c @@ -32,6 +32,7 @@ enum aspeed_smc_flash_type { }; struct aspeed_smc_chip; +struct aspeed_smc_controller; struct aspeed_smc_info { u32 maxsize; /* maximum size of chip window */ @@ -43,6 +44,10 @@ struct aspeed_smc_info { void (*set_4b)(struct aspeed_smc_chip *chip); int (*optimize_read)(struct aspeed_smc_chip *chip, u32 max_freq); + u32 (*segment_start)(struct aspeed_smc_controller *controller, u32 reg); + u32 (*segment_end)(struct aspeed_smc_controller *controller, u32 reg); + u32 (*segment_reg)(struct aspeed_smc_controller *controller, + u32 start, u32 end); }; static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip); @@ -50,6 +55,13 @@ static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip); static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip, u32 max_freq); +static u32 aspeed_smc_segment_start(struct aspeed_smc_controller *controller, + u32 reg); +static u32 aspeed_smc_segment_end(struct aspeed_smc_controller *controller, + u32 reg); +static u32 aspeed_smc_segment_reg(struct aspeed_smc_controller *controller, + u32 start, u32 end); + static const struct aspeed_smc_info fmc_2400_info = { .maxsize = 64 * 1024 * 1024, .nce = 5, @@ -59,6 +71,9 @@ static const struct aspeed_smc_info fmc_2400_info = { .timing = 0x94, .set_4b = aspeed_smc_chip_set_4b, .optimize_read = aspeed_smc_optimize_read, + .segment_start = aspeed_smc_segment_start, + .segment_end = aspeed_smc_segment_end, + .segment_reg = aspeed_smc_segment_reg, }; static const struct aspeed_smc_info spi_2400_info = { @@ -70,6 +85,7 @@ static const struct aspeed_smc_info spi_2400_info = { .timing = 0x14, .set_4b = aspeed_smc_chip_set_4b_spi_2400, .optimize_read = aspeed_smc_optimize_read, + /* No segment registers */ }; static const struct aspeed_smc_info fmc_2500_info = { @@ -81,6 +97,9 @@ static const struct aspeed_smc_info fmc_2500_info = { .timing = 0x94, .set_4b = aspeed_smc_chip_set_4b, .optimize_read = aspeed_smc_optimize_read, + .segment_start = aspeed_smc_segment_start, + .segment_end = aspeed_smc_segment_end, + .segment_reg = aspeed_smc_segment_reg, }; static const struct aspeed_smc_info spi_2500_info = { @@ -92,6 +111,9 @@ static const struct aspeed_smc_info spi_2500_info = { .timing = 0x94, .set_4b = aspeed_smc_chip_set_4b, .optimize_read = aspeed_smc_optimize_read, + .segment_start = aspeed_smc_segment_start, + .segment_end = aspeed_smc_segment_end, + .segment_reg = aspeed_smc_segment_reg, }; enum aspeed_smc_ctl_reg_value { @@ -201,22 +223,34 @@ struct aspeed_smc_controller { (CONTROL_AAF_MODE | CONTROL_CE_INACTIVE_MASK | CONTROL_CLK_DIV4 | \ CONTROL_CLOCK_FREQ_SEL_MASK | CONTROL_LSB_FIRST | CONTROL_CLOCK_MODE_3) -/* - * The Segment Register uses a 8MB unit to encode the start address - * and the end address of the mapping window of a flash SPI slave : - * - * | byte 1 | byte 2 | byte 3 | byte 4 | - * +--------+--------+--------+--------+ - * | end | start | 0 | 0 | - */ #define SEGMENT_ADDR_REG0 0x30 -#define SEGMENT_ADDR_START(_r) ((((_r) >> 16) & 0xFF) << 23) -#define SEGMENT_ADDR_END(_r) ((((_r) >> 24) & 0xFF) << 23) -#define SEGMENT_ADDR_VALUE(start, end) \ - (((((start) >> 23) & 0xFF) << 16) | ((((end) >> 23) & 0xFF) << 24)) #define SEGMENT_ADDR_REG(controller, cs) \ ((controller)->regs + SEGMENT_ADDR_REG0 + (cs) * 4) +/* + * The Segment Registers of the AST2400 and AST2500 have a 8MB + * unit. The address range of a flash SPI slave is encoded with + * absolute addresses which should be part of the overall controller + * window. + */ +static u32 aspeed_smc_segment_start(struct aspeed_smc_controller *controller, + u32 reg) +{ + return ((reg >> 16) & 0xFF) << 23; +} + +static u32 aspeed_smc_segment_end(struct aspeed_smc_controller *controller, + u32 reg) +{ + return ((reg >> 24) & 0xFF) << 23; +} + +static u32 aspeed_smc_segment_reg(struct aspeed_smc_controller *controller, + u32 start, u32 end) +{ + return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24); +} + /* * Switch to turn off read optimisation if needed */ @@ -519,16 +553,19 @@ static void __iomem *aspeed_smc_chip_base(struct aspeed_smc_chip *chip, struct resource *res) { struct aspeed_smc_controller *controller = chip->controller; + const struct aspeed_smc_info *info = controller->info; u32 offset = 0; u32 reg; - if (controller->info->nce > 1) { + if (info->nce > 1) { reg = readl(SEGMENT_ADDR_REG(controller, chip->cs)); - if (SEGMENT_ADDR_START(reg) >= SEGMENT_ADDR_END(reg)) + if (info->segment_start(controller, reg) >= + info->segment_end(controller, reg)) { return NULL; + } - offset = SEGMENT_ADDR_START(reg) - res->start; + offset = info->segment_start(controller, reg) - res->start; } return controller->ahb_base + offset; @@ -538,6 +575,7 @@ static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start, u32 size) { struct aspeed_smc_controller *controller = chip->controller; + const struct aspeed_smc_info *info = controller->info; void __iomem *seg_reg; u32 seg_oldval, seg_newval, end; u32 ahb_base_phy = controller->ahb_base_phy; @@ -551,7 +589,7 @@ static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start, * previous segment */ if (!size) - size = SEGMENT_ADDR_END(seg_oldval) - start; + size = info->segment_end(controller, seg_oldval) - start; /* * The segment cannot exceed the maximum window size of the @@ -564,7 +602,7 @@ static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start, } end = start + size; - seg_newval = SEGMENT_ADDR_VALUE(start, end); + seg_newval = info->segment_reg(controller, start, end); writel(seg_newval, seg_reg); /* @@ -575,8 +613,8 @@ static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start, if (seg_newval != readl(seg_reg)) { dev_err(chip->nor.dev, "CE%d window invalid", cs); writel(seg_oldval, seg_reg); - start = SEGMENT_ADDR_START(seg_oldval); - end = SEGMENT_ADDR_END(seg_oldval); + start = info->segment_start(controller, seg_oldval); + end = info->segment_end(controller, seg_oldval); size = end - start; } @@ -639,7 +677,7 @@ static u32 aspeed_smc_chip_set_segment(struct aspeed_smc_chip *chip) if (chip->cs) { u32 prev = readl(SEGMENT_ADDR_REG(controller, chip->cs - 1)); - start = SEGMENT_ADDR_END(prev); + start = controller->info->segment_end(controller, prev); } else { start = ahb_base_phy; }