| Message ID | 20191025135144.8805-1-christoffer.dall@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: arm64: Don't set HCR_EL2.TVM when S2FWB is supported | expand |
[correcitng Marc's address] On Fri, Oct 25, 2019 at 03:51:44PM +0200, Christoffer Dall wrote: > On CPUs that support S2FWB (Armv8.4+), KVM configures the stage 2 page > tables to override the memory attributes of memory accesses, regardless > of the stage 1 page table configurations, and also when the stage 1 MMU > is turned off. This results in all memory accesses to RAM being > cacheable, including during early boot of the guest. > > On CPUs without this feature, memory accesses were non-cacheable during > boot until the guest turned on the stage 1 MMU, and we had to detect > when the guest turned on the MMU, such that we could invalidate all cache > entries and ensure a consistent view of memory with the MMU turned on. > When the guest turned on the caches, we would call stage2_flush_vm() > from kvm_toggle_cache(). > > However, stage2_flush_vm() walks all the stage 2 tables, and calls > __kvm_flush-dcache_pte, which on a system with S2FWD does ... absolutely > nothing. > > We can avoid that whole song and dance, and simply not set TVM when > creating a VM on a systme that has S2FWB. Typo: s/systme/system/ > Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Alexandru Elisei <alexandru.elisei@arm.com> > --- > I was only able to test this on the model with cache modeling enabled, > but even removing TVM from HCR_EL2 without having FWB also worked with > that setup, so the testing of this has been light. It seems like it > should obviously work, but it would be good if someone with access to > appropriate hardware could give this a spin. I'm afraid I don't have such hardware to test on, but this does make sense to me based on my understanding of the behaviour of FWB. > arch/arm64/include/asm/kvm_emulate.h | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h > index d69c1efc63e7..41820c3e70b8 100644 > --- a/arch/arm64/include/asm/kvm_emulate.h > +++ b/arch/arm64/include/asm/kvm_emulate.h > @@ -53,8 +53,10 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) > /* trap error record accesses */ > vcpu->arch.hcr_el2 |= HCR_TERR; > } > - if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) > + if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) { > + vcpu->arch.hcr_el2 &= ~HCR_TVM; > vcpu->arch.hcr_el2 |= HCR_FWB; > + } Given we also later nuke this fit for !FWB, maybe we want to take it out of HCR_GUEST_FLAGS and have: if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) vcpu->arch.hcr_el2 |= HCR_FWB; else vcpu->arch.hcr_el2 |= HCR_TVM; Either way: Reviewed-by: Mark Rutlamd <mark.rutland@arm.com> Thanks, Mark. > > if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) > vcpu->arch.hcr_el2 &= ~HCR_RW; > -- > 2.18.0 >
diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index d69c1efc63e7..41820c3e70b8 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -53,8 +53,10 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) /* trap error record accesses */ vcpu->arch.hcr_el2 |= HCR_TERR; } - if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) + if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) { + vcpu->arch.hcr_el2 &= ~HCR_TVM; vcpu->arch.hcr_el2 |= HCR_FWB; + } if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) vcpu->arch.hcr_el2 &= ~HCR_RW;
On CPUs that support S2FWB (Armv8.4+), KVM configures the stage 2 page tables to override the memory attributes of memory accesses, regardless of the stage 1 page table configurations, and also when the stage 1 MMU is turned off. This results in all memory accesses to RAM being cacheable, including during early boot of the guest. On CPUs without this feature, memory accesses were non-cacheable during boot until the guest turned on the stage 1 MMU, and we had to detect when the guest turned on the MMU, such that we could invalidate all cache entries and ensure a consistent view of memory with the MMU turned on. When the guest turned on the caches, we would call stage2_flush_vm() from kvm_toggle_cache(). However, stage2_flush_vm() walks all the stage 2 tables, and calls __kvm_flush-dcache_pte, which on a system with S2FWD does ... absolutely nothing. We can avoid that whole song and dance, and simply not set TVM when creating a VM on a systme that has S2FWB. Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Alexandru Elisei <alexandru.elisei@arm.com> --- I was only able to test this on the model with cache modeling enabled, but even removing TVM from HCR_EL2 without having FWB also worked with that setup, so the testing of this has been light. It seems like it should obviously work, but it would be good if someone with access to appropriate hardware could give this a spin. arch/arm64/include/asm/kvm_emulate.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)