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Fri, 1 Nov 2019 08:36:17 +0000 Received: from DB7PR04MB4618.eurprd04.prod.outlook.com ([fe80::79f1:61a7:4076:8679]) by DB7PR04MB4618.eurprd04.prod.outlook.com ([fe80::79f1:61a7:4076:8679%3]) with mapi id 15.20.2367.031; Fri, 1 Nov 2019 08:36:17 +0000 From: Joakim Zhang To: "will@kernel.org" , "mark.rutland@arm.com" , "robin.murphy@arm.com" Subject: [PATCH V3 3/4] perf/imx_ddr: Add enhanced AXI ID filter support Thread-Topic: [PATCH V3 3/4] perf/imx_ddr: Add enhanced AXI ID filter support Thread-Index: AQHVkI9tmOl/phINXEWndRHoKw3IpQ== Date: Fri, 1 Nov 2019 08:36:16 +0000 Message-ID: <20191101083317.29510-3-qiangqing.zhang@nxp.com> References: <20191101083317.29510-1-qiangqing.zhang@nxp.com> In-Reply-To: <20191101083317.29510-1-qiangqing.zhang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.17.1 x-clientproxiedby: SG2PR04CA0156.apcprd04.prod.outlook.com (2603:1096:4::18) To DB7PR04MB4618.eurprd04.prod.outlook.com (2603:10a6:5:38::23) authentication-results: spf=none (sender IP is ) smtp.mailfrom=qiangqing.zhang@nxp.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB7PR04MB5948; H:DB7PR04MB4618.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: JTeGgu5aUXZQmivs/eJDrqXvQmjvEvUQGE+ql7AhORw2dZ+JW0dJzY/JT72/eYJpI55+FfA9Fbj707Ni124i09cY081c4tDdZae9T19H1XXSGhY/2+ccRPek4ENGwI4xISWfIMY9s5dlESrO2TifvQHktbL6oh2bmQgUg3WD2eacgQ3Qov/1N8HSY0zaRho08V/rdHGH5K7uBPUcnYmIoeTwXSyxMIbddcHYTPT4t9k1ybRL+Qg1cfvZm+Y/8M/9jD30aL15tnvFminv9qVExadw3qKs6Tm0jD4Lm1TBaYgQ0cMfIe1xSSQVXkwlWVs32g0p8nyudVta44ZShrozSX8Uvp12PCEzGmiv1keEeJzqhaxMWHPaCyVslQcUUbT6ZokRV+ZtRdihwjAdfK9sDpI6Qczv32a667MzUp5rrHPudX72+9t5ZNMs/u7+mmXu MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: e792dd91-2a88-4315-0202-08d75ea68fdb X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Nov 2019 08:36:17.1608 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 7JSWhXKa4pB0B8C0JuOBboE7bZGMG1nVNifnP4HdvOoOfAevF8xxFe3qHApA/SaXJq436TJKuBIzTq+in1hocg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB5948 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191101_013620_860038_4B073371 X-CRM114-Status: GOOD ( 13.28 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.15.51 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Li , dl-linux-imx , "linux-arm-kernel@lists.infradead.org" , Joakim Zhang Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org With DDR_CAP_AXI_ID_FILTER quirk, indicating HW supports AXI ID filter which only can get bursts from DDR transaction, i.e. DDR read/write requests. This patch add DDR_CAP_AXI_ID_ENHANCED_FILTER quirk, indicating HW supports AXI ID filter which can get bursts and bytes from DDR transaction at the same time. We hope PMU always return bytes in the driver due to it is more meaningful for users. Signed-off-by: Joakim Zhang --- Changelog: V1->V2: * use ddr_perf_is_filtered() helper to simply the code. * improve the commit message. V2->V3: * change definition of DDR_CAP_AXI_ID_FILTER_ENHANCED quirk. * add ddr_perf_is_enhanced_filtered() helper. --- drivers/perf/fsl_imx8_ddr_perf.c | 63 +++++++++++++++++++++----------- 1 file changed, 42 insertions(+), 21 deletions(-) diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index ce7345745b42..2a3966d059e7 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -45,7 +45,8 @@ static DEFINE_IDA(ddr_ida); /* DDR Perf hardware feature */ -#define DDR_CAP_AXI_ID_FILTER 0x1 /* support AXI ID filter */ +#define DDR_CAP_AXI_ID_FILTER 0x1 /* support AXI ID filter */ +#define DDR_CAP_AXI_ID_FILTER_ENHANCED 0x3 /* support enhanced AXI ID filter */ struct fsl_ddr_devtype_data { unsigned int quirks; /* quirks needed for different DDR Perf core */ @@ -178,6 +179,36 @@ static const struct attribute_group *attr_groups[] = { NULL, }; +static bool ddr_perf_is_filtered(struct perf_event *event) +{ + return event->attr.config == 0x41 || event->attr.config == 0x42; +} + +static u32 ddr_perf_filter_val(struct perf_event *event) +{ + return event->attr.config1; +} + +static bool ddr_perf_filters_compatible(struct perf_event *a, + struct perf_event *b) +{ + if (!ddr_perf_is_filtered(a)) + return true; + if (!ddr_perf_is_filtered(b)) + return true; + return ddr_perf_filter_val(a) == ddr_perf_filter_val(b); +} + +static bool ddr_perf_is_enhanced_filtered(struct perf_event *event) +{ + unsigned int filt; + struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); + + filt = pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED; + return (filt == DDR_CAP_AXI_ID_FILTER_ENHANCED) && + ddr_perf_is_filtered(event); +} + static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event) { int i; @@ -209,27 +240,17 @@ static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter) static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter) { - return readl_relaxed(pmu->base + COUNTER_READ + counter * 4); -} - -static bool ddr_perf_is_filtered(struct perf_event *event) -{ - return event->attr.config == 0x41 || event->attr.config == 0x42; -} + struct perf_event *event = pmu->events[counter]; + void __iomem *base = pmu->base; -static u32 ddr_perf_filter_val(struct perf_event *event) -{ - return event->attr.config1; -} - -static bool ddr_perf_filters_compatible(struct perf_event *a, - struct perf_event *b) -{ - if (!ddr_perf_is_filtered(a)) - return true; - if (!ddr_perf_is_filtered(b)) - return true; - return ddr_perf_filter_val(a) == ddr_perf_filter_val(b); + /* + * return bytes instead of bursts from ddr transaction for + * axid-read and axid-write event if PMU core supports enhanced + * filter. + */ + base += ddr_perf_is_enhanced_filtered(event) ? COUNTER_DPCR1 : + COUNTER_READ; + return readl_relaxed(base + counter * 4); } static int ddr_perf_event_init(struct perf_event *event)