diff mbox series

arm64: dts: ls1028a: fix reboot node

Message ID 20191123000709.13162-1-michael@walle.cc (mailing list archive)
State New, archived
Headers show
Series arm64: dts: ls1028a: fix reboot node | expand

Commit Message

Michael Walle Nov. 23, 2019, 12:07 a.m. UTC
The reboot register isn't located inside the DCFG controller, but in its
own RST controller. Fix it.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

Comments

Shawn Guo Dec. 9, 2019, 3:46 a.m. UTC | #1
On Sat, Nov 23, 2019 at 01:07:09AM +0100, Michael Walle wrote:
> The reboot register isn't located inside the DCFG controller, but in its
> own RST controller. Fix it.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

Do we need a Fixes tag?

@Leo, looks good to you?

Shawn

> ---
>  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index 72b9a75976a1..dc75534a4754 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -102,7 +102,7 @@
>  
>  	reboot {
>  		compatible ="syscon-reboot";
> -		regmap = <&dcfg>;
> +		regmap = <&rst>;
>  		offset = <0xb0>;
>  		mask = <0x02>;
>  	};
> @@ -161,6 +161,12 @@
>  			big-endian;
>  		};
>  
> +		rst: syscon@1e60000 {
> +			compatible = "fsl,ls1028a-rst", "syscon";
> +			reg = <0x0 0x1e60000 0x0 0x10000>;
> +			little-endian;
> +		};
> +
>  		scfg: syscon@1fc0000 {
>  			compatible = "fsl,ls1028a-scfg", "syscon";
>  			reg = <0x0 0x1fc0000 0x0 0x10000>;
> -- 
> 2.20.1
>
Shawn Guo Dec. 9, 2019, 3:47 a.m. UTC | #2
On Sat, Nov 23, 2019 at 01:07:09AM +0100, Michael Walle wrote:
> The reboot register isn't located inside the DCFG controller, but in its
> own RST controller. Fix it.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
>  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index 72b9a75976a1..dc75534a4754 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -102,7 +102,7 @@
>  
>  	reboot {
>  		compatible ="syscon-reboot";
> -		regmap = <&dcfg>;
> +		regmap = <&rst>;
>  		offset = <0xb0>;
>  		mask = <0x02>;
>  	};
> @@ -161,6 +161,12 @@
>  			big-endian;
>  		};
>  
> +		rst: syscon@1e60000 {
> +			compatible = "fsl,ls1028a-rst", "syscon";

Compatible "fsl,ls1028a-rst" seems undocumented?

Shawn

> +			reg = <0x0 0x1e60000 0x0 0x10000>;
> +			little-endian;
> +		};
> +
>  		scfg: syscon@1fc0000 {
>  			compatible = "fsl,ls1028a-scfg", "syscon";
>  			reg = <0x0 0x1fc0000 0x0 0x10000>;
> -- 
> 2.20.1
>
Michael Walle Dec. 9, 2019, 9:02 a.m. UTC | #3
Am 2019-12-09 04:47, schrieb Shawn Guo:
> On Sat, Nov 23, 2019 at 01:07:09AM +0100, Michael Walle wrote:
>> The reboot register isn't located inside the DCFG controller, but in 
>> its
>> own RST controller. Fix it.
>> 
>> Signed-off-by: Michael Walle <michael@walle.cc>
>> ---
>>  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 8 +++++++-
>>  1 file changed, 7 insertions(+), 1 deletion(-)
>> 
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
>> b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
>> index 72b9a75976a1..dc75534a4754 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
>> @@ -102,7 +102,7 @@
>> 
>>  	reboot {
>>  		compatible ="syscon-reboot";
>> -		regmap = <&dcfg>;
>> +		regmap = <&rst>;
>>  		offset = <0xb0>;
>>  		mask = <0x02>;
>>  	};
>> @@ -161,6 +161,12 @@
>>  			big-endian;
>>  		};
>> 
>> +		rst: syscon@1e60000 {
>> +			compatible = "fsl,ls1028a-rst", "syscon";
> 
> Compatible "fsl,ls1028a-rst" seems undocumented?

it is the same with fsl,ls1028a-scfg and fsl,ls1028a-dcfg. So maybe I 
should just drop the "fsl,ls1028a-rst". What do you think?

-michael

> 
> Shawn
> 
>> +			reg = <0x0 0x1e60000 0x0 0x10000>;
>> +			little-endian;
>> +		};
>> +
>>  		scfg: syscon@1fc0000 {
>>  			compatible = "fsl,ls1028a-scfg", "syscon";
>>  			reg = <0x0 0x1fc0000 0x0 0x10000>;
>> --
>> 2.20.1
>>
Shawn Guo Dec. 11, 2019, 2:17 a.m. UTC | #4
On Mon, Dec 09, 2019 at 10:02:02AM +0100, Michael Walle wrote:
> Am 2019-12-09 04:47, schrieb Shawn Guo:
> >On Sat, Nov 23, 2019 at 01:07:09AM +0100, Michael Walle wrote:
> >>The reboot register isn't located inside the DCFG controller,
> >>but in its
> >>own RST controller. Fix it.
> >>
> >>Signed-off-by: Michael Walle <michael@walle.cc>
> >>---
> >> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 8 +++++++-
> >> 1 file changed, 7 insertions(+), 1 deletion(-)
> >>
> >>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> >>b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> >>index 72b9a75976a1..dc75534a4754 100644
> >>--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> >>+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> >>@@ -102,7 +102,7 @@
> >>
> >> 	reboot {
> >> 		compatible ="syscon-reboot";
> >>-		regmap = <&dcfg>;
> >>+		regmap = <&rst>;
> >> 		offset = <0xb0>;
> >> 		mask = <0x02>;
> >> 	};
> >>@@ -161,6 +161,12 @@
> >> 			big-endian;
> >> 		};
> >>
> >>+		rst: syscon@1e60000 {
> >>+			compatible = "fsl,ls1028a-rst", "syscon";
> >
> >Compatible "fsl,ls1028a-rst" seems undocumented?
> 
> it is the same with fsl,ls1028a-scfg and fsl,ls1028a-dcfg. So maybe
> I should just drop the "fsl,ls1028a-rst". What do you think?

Drop it or document it.  I'm fine with either way.

Shawn
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 72b9a75976a1..dc75534a4754 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -102,7 +102,7 @@ 
 
 	reboot {
 		compatible ="syscon-reboot";
-		regmap = <&dcfg>;
+		regmap = <&rst>;
 		offset = <0xb0>;
 		mask = <0x02>;
 	};
@@ -161,6 +161,12 @@ 
 			big-endian;
 		};
 
+		rst: syscon@1e60000 {
+			compatible = "fsl,ls1028a-rst", "syscon";
+			reg = <0x0 0x1e60000 0x0 0x10000>;
+			little-endian;
+		};
+
 		scfg: syscon@1fc0000 {
 			compatible = "fsl,ls1028a-scfg", "syscon";
 			reg = <0x0 0x1fc0000 0x0 0x10000>;