diff mbox series

ARM: dts: ux500: Drop pulls on I2C buses

Message ID 20191126123116.56244-1-linus.walleij@linaro.org (mailing list archive)
State Mainlined
Commit 27e7c033d3b4101bc3b9a344265de5ae89e09b42
Headers show
Series ARM: dts: ux500: Drop pulls on I2C buses | expand

Commit Message

Linus Walleij Nov. 26, 2019, 12:31 p.m. UTC
The I2C block in the Ux500 uses internal pull-ups on the
SoC, in fact it has to: in HS mode, the I2C block will need
to autonomously take control over the pull-up line to do
its job. This can be clearly seen from the SoC manual which
states that the silicon has a line named "en_cspu_hs" which
enables current source pull-up for high speed mode. Another
hint is that the vendor code tree never enabled the pull
up on these lines, despite being deployed on boards that
lack external pull-up resistors.

Tested on the Ux500 reference designs without any problems.

Cc: Stephan Gerhold <stephan@gerhold.net>
Reported-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

Comments

Stephan Gerhold Nov. 26, 2019, 5:59 p.m. UTC | #1
On Tue, Nov 26, 2019 at 01:31:16PM +0100, Linus Walleij wrote:
> The I2C block in the Ux500 uses internal pull-ups on the
> SoC, in fact it has to: in HS mode, the I2C block will need
> to autonomously take control over the pull-up line to do
> its job. This can be clearly seen from the SoC manual which
> states that the silicon has a line named "en_cspu_hs" which
> enables current source pull-up for high speed mode. Another
> hint is that the vendor code tree never enabled the pull
> up on these lines, despite being deployed on boards that
> lack external pull-up resistors.
> 
> Tested on the Ux500 reference designs without any problems.
> 
> Cc: Stephan Gerhold <stephan@gerhold.net>
> Reported-by: Stephan Gerhold <stephan@gerhold.net>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Reviewed-by: Stephan Gerhold <stephan@gerhold.net>

FWIW, on samsung,golden:
Tested-by: Stephan Gerhold <stephan@gerhold.net>

> ---
>  arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
> index e85a08ad2ea7..7bf7a2d34cbc 100644
> --- a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
> @@ -130,7 +130,7 @@
>  			};
>  			default_cfg1 {
>  				pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
> -				ste,config = <&in_pu>;
> +				ste,config = <&in_nopull>;
>  			};
>  		};
>  
> @@ -150,7 +150,7 @@
>  			};
>  			default_cfg1 {
>  				pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
> -				ste,config = <&in_pu>;
> +				ste,config = <&in_nopull>;
>  			};
>  		};
>  
> @@ -170,7 +170,7 @@
>  			};
>  			default_cfg1 {
>  				pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
> -				ste,config = <&in_pu>;
> +				ste,config = <&in_nopull>;
>  			};
>  		};
>  
> @@ -190,7 +190,7 @@
>  			};
>  			default_cfg1 {
>  				pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
> -				ste,config = <&in_pu>;
> +				ste,config = <&in_nopull>;
>  			};
>  		};
>  
> @@ -214,7 +214,7 @@
>  			};
>  			default_cfg1 {
>  				pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
> -				ste,config = <&in_pu>;
> +				ste,config = <&in_nopull>;
>  			};
>  		};
>  
> -- 
> 2.23.0
>
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
index e85a08ad2ea7..7bf7a2d34cbc 100644
--- a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
@@ -130,7 +130,7 @@ 
 			};
 			default_cfg1 {
 				pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
-				ste,config = <&in_pu>;
+				ste,config = <&in_nopull>;
 			};
 		};
 
@@ -150,7 +150,7 @@ 
 			};
 			default_cfg1 {
 				pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
-				ste,config = <&in_pu>;
+				ste,config = <&in_nopull>;
 			};
 		};
 
@@ -170,7 +170,7 @@ 
 			};
 			default_cfg1 {
 				pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
-				ste,config = <&in_pu>;
+				ste,config = <&in_nopull>;
 			};
 		};
 
@@ -190,7 +190,7 @@ 
 			};
 			default_cfg1 {
 				pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
-				ste,config = <&in_pu>;
+				ste,config = <&in_nopull>;
 			};
 		};
 
@@ -214,7 +214,7 @@ 
 			};
 			default_cfg1 {
 				pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
-				ste,config = <&in_pu>;
+				ste,config = <&in_nopull>;
 			};
 		};