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Mon, 9 Dec 2019 04:36:04 -0500 (EST) From: Maxime Ripard To: Mark Rutland , Rob Herring , Frank Rowand Subject: [PATCH 3/3] dt-bindings: clocks: Convert Allwinner A80 DE clocks to a schema Date: Mon, 9 Dec 2019 10:35:58 +0100 Message-Id: <20191209093558.50940-3-maxime@cerno.tech> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191209093558.50940-1-maxime@cerno.tech> References: <20191209093558.50940-1-maxime@cerno.tech> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191209_013605_457301_834B1D62 X-CRM114-Status: GOOD ( 12.30 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [66.111.4.221 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Mike Turquette , Stephen Boyd , Maxime Ripard , Chen-Yu Tsai , Maxime Ripard , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The Allwinner A80 SoC has a display clocks controller that is supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Signed-off-by: Maxime Ripard Reviewed-by: Stephen Boyd --- .../clock/allwinner,sun9i-a80-de-clks.yaml | 67 +++++++++++++++++++ .../devicetree/bindings/clock/sun9i-de.txt | 28 -------- 2 files changed, 67 insertions(+), 28 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-de-clks.yaml delete mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-de-clks.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-de-clks.yaml new file mode 100644 index 000000000000..a82c7c7e942b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-de-clks.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 Display Engine Clock Controller Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-de-clks + + reg: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: RAM Bus Clock + - description: Module Clock + + clock-names: + items: + - const: mod + - const: dram + - const: bus + + resets: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include + #include + + de_clocks: clock@3000000 { + compatible = "allwinner,sun9i-a80-de-clks"; + reg = <0x03000000 0x30>; + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; + clock-names = "mod", "dram", "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt deleted file mode 100644 index fb18f327b97a..000000000000 --- a/Documentation/devicetree/bindings/clock/sun9i-de.txt +++ /dev/null @@ -1,28 +0,0 @@ -Allwinner A80 Display Engine Clock Control Binding --------------------------------------------------- - -Required properties : -- compatible: must contain one of the following compatibles: - - "allwinner,sun9i-a80-de-clks" - -- reg: Must contain the registers base address and length -- clocks: phandle to the clocks feeding the display engine subsystem. - Three are needed: - - "mod": the display engine module clock - - "dram": the DRAM bus clock for the system - - "bus": the bus clock for the whole display engine subsystem -- clock-names: Must contain the clock names described just above -- resets: phandle to the reset control for the display engine subsystem. -- #clock-cells : must contain 1 -- #reset-cells : must contain 1 - -Example: -de_clocks: clock@3000000 { - compatible = "allwinner,sun9i-a80-de-clks"; - reg = <0x03000000 0x30>; - clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; - clock-names = "mod", "dram", "bus"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; -};