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Thu, 19 Dec 2019 04:20:05 -0500 (EST) From: Maxime Ripard To: Chen-Yu Tsai , Maxime Ripard Subject: [PATCH 2/2] drm/sun4i: drc: Make sure we enforce the clock rate Date: Thu, 19 Dec 2019 10:20:00 +0100 Message-Id: <20191219092000.949052-2-maxime@cerno.tech> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191219092000.949052-1-maxime@cerno.tech> References: <20191219092000.949052-1-maxime@cerno.tech> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191219_012009_870780_C98725B0 X-CRM114-Status: UNSURE ( 9.89 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [64.147.123.24 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Kocialkowski , linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, Maxime Ripard Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The DRC needs to run at 300MHz to be functional. This was done so far using assigned-clocks in the device tree, but that is easy to forget, and dosen't provide any other guarantee than the rate is going to be roughly the one requested at probe time. Therefore it's pretty fragile, so let's just use the exclusive clock API to enforce it. Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai --- drivers/gpu/drm/sun4i/sun6i_drc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun6i_drc.c b/drivers/gpu/drm/sun4i/sun6i_drc.c index f7ab72244796..ddb52da90103 100644 --- a/drivers/gpu/drm/sun4i/sun6i_drc.c +++ b/drivers/gpu/drm/sun4i/sun6i_drc.c @@ -57,6 +57,7 @@ static int sun6i_drc_bind(struct device *dev, struct device *master, goto err_disable_bus_clk; } clk_prepare_enable(drc->mod_clk); + clk_set_rate_exclusive(drc->mod_clk, 300000000); return 0; @@ -72,6 +73,7 @@ static void sun6i_drc_unbind(struct device *dev, struct device *master, { struct sun6i_drc *drc = dev_get_drvdata(dev); + clk_rate_exclusive_put(drc->mod_clk); clk_disable_unprepare(drc->mod_clk); clk_disable_unprepare(drc->bus_clk); reset_control_assert(drc->reset);