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[73.69.118.222]) by smtp.gmail.com with ESMTPSA id f97sm17384185qtb.18.2020.01.02.13.14.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2020 13:14:06 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk, andrew.cooper3@citrix.com, julien@xen.org Subject: [PATCH v5 4/6] arm64: remove __asm_flush_icache_range Date: Thu, 2 Jan 2020 16:13:55 -0500 Message-Id: <20200102211357.8042-5-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200102211357.8042-1-pasha.tatashin@soleen.com> References: <20200102211357.8042-1-pasha.tatashin@soleen.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200102_131408_628193_E09ECB8D X-CRM114-Status: GOOD ( 11.97 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org __asm_flush_icache_range is an alias to __asm_flush_cache_user_range, but now that these functions are called from C wrappers the fall through can instead be done at a higher level. Remove the __asm_flush_icache_range alias in assembly, and instead call __flush_cache_user_range() from __flush_icache_range(). Signed-off-by: Pavel Tatashin --- arch/arm64/include/asm/cacheflush.h | 5 +---- arch/arm64/mm/cache.S | 14 -------------- arch/arm64/mm/flush.c | 2 +- 3 files changed, 2 insertions(+), 19 deletions(-) diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index cb00c61e0bde..047af338ba15 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -61,7 +61,6 @@ * - kaddr - page address * - size - region size */ -extern void __asm_flush_icache_range(unsigned long start, unsigned long end); extern long __asm_flush_cache_user_range(unsigned long start, unsigned long end); extern int __asm_invalidate_icache_range(unsigned long start, @@ -87,9 +86,7 @@ static inline long __flush_cache_user_range(unsigned long start, static inline void __flush_icache_range(unsigned long start, unsigned long end) { - uaccess_ttbr0_enable(); - __asm_flush_icache_range(start, end); - uaccess_ttbr0_disable(); + __flush_cache_user_range(start, end); } static inline int invalidate_icache_range(unsigned long start, diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 602b9aa8603a..1981cbaf5d92 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -14,19 +14,6 @@ #include #include -/* - * __asm_flush_icache_range(start,end) - * - * Ensure that the I and D caches are coherent within specified region. - * This is typically used when code has been written to a memory region, - * and will be executed. - * - * - start - virtual start address of region - * - end - virtual end address of region - */ -ENTRY(__asm_flush_icache_range) - /* FALLTHROUGH */ - /* * __asm_flush_cache_user_range(start,end) * @@ -62,7 +49,6 @@ alternative_else_nop_endif 1: ret 9: mov x0, #-EFAULT b 1b -ENDPROC(__asm_flush_icache_range) ENDPROC(__asm_flush_cache_user_range) /* diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index b23f34d23f31..61521285f27d 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -75,7 +75,7 @@ EXPORT_SYMBOL(flush_dcache_page); /* * Additional functions defined in assembly. */ -EXPORT_SYMBOL(__asm_flush_icache_range); +EXPORT_SYMBOL(__asm_flush_cache_user_range); #ifdef CONFIG_ARCH_HAS_PMEM_API void arch_wb_cache_pmem(void *addr, size_t size)