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[81.140.166.164]) by smtp.gmail.com with ESMTPSA id a16sm8545544wrt.37.2020.01.09.08.05.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 08:05:46 -0800 (PST) From: Julien Thierry To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC v5 23/57] objtool: arm64: Decode logical data processing instructions Date: Thu, 9 Jan 2020 16:02:26 +0000 Message-Id: <20200109160300.26150-24-jthierry@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200109160300.26150-1-jthierry@redhat.com> References: <20200109160300.26150-1-jthierry@redhat.com> MIME-Version: 1.0 X-MC-Unique: K22vHRlePwea3mPZL3Jo_Q-1 X-Mimecast-Spam-Score: 0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200109_080550_622103_2D610A18 X-CRM114-Status: GOOD ( 12.03 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [207.211.31.120 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Julien Thierry , peterz@infradead.org, catalin.marinas@arm.com, raphael.gault@arm.com, jpoimboe@redhat.com, will@kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Decode instructions performing logical operations with immediate values. Create a stack operation for and operation targeting the stack pointer. Since OP_SRC_AND assumes the source and destination register are the same, add a register assignment operation when the source operand of the logical instruction is not the stack pointer. Suggested-by: Raphael Gault Signed-off-by: Julien Thierry --- tools/objtool/arch/arm64/decode.c | 58 +++++++++++++++++++ .../objtool/arch/arm64/include/insn_decode.h | 3 + 2 files changed, 61 insertions(+) diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c index d240f29a2390..a30c3294cc21 100644 --- a/tools/objtool/arch/arm64/decode.c +++ b/tools/objtool/arch/arm64/decode.c @@ -160,6 +160,7 @@ static arm_decode_class aarch64_insn_dp_imm_decode_table[NR_DP_IMM_SUBCLASS] = { [0 ... INSN_PCREL] = arm_decode_pcrel, [INSN_ADD_SUB] = arm_decode_add_sub, [INSN_ADD_TAG] = arm_decode_add_sub_tags, + [INSN_LOGICAL] = arm_decode_logical, [INSN_MOVE_WIDE] = arm_decode_move_wide, [INSN_BITFIELD] = arm_decode_bitfield, [INSN_EXTRACT] = arm_decode_extract, @@ -273,6 +274,63 @@ int arm_decode_add_sub_tags(u32 instr, enum insn_type *type, return 0; } +int arm_decode_logical(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + unsigned char sf = 0, opc = 0, N = 0; + unsigned char imms = 0, immr = 0, rn = 0, rd = 0; + struct stack_op *op; + + rd = instr & ONES(5); + rn = (instr >> 5) & ONES(5); + + imms = (instr >> 10) & ONES(6); + immr = (instr >> 16) & ONES(6); + + N = EXTRACT_BIT(instr, 22); + opc = (instr >> 29) & ONES(2); + sf = EXTRACT_BIT(instr, 31); + + if (N == 1 && sf == 0) + return arm_decode_unknown(instr, type, immediate, ops_list); + + *type = INSN_OTHER; + *immediate = (decode_bit_masks(N, imms, immr, true) >> 64); + + if (opc & 1) + return 0; + + if (rd != CFI_SP) + return 0; + + *type = INSN_STACK; + + if (rn != CFI_SP) { + op = calloc(1, sizeof(*op)); + list_add_tail(&op->list, ops_list); + + op->dest.type = OP_DEST_REG; + op->dest.offset = 0; + op->dest.reg = rd; + op->src.type = OP_SRC_REG; + op->src.offset = 0; + op->src.reg = rn; + } + + op = calloc(1, sizeof(*op)); + list_add_tail(&op->list, ops_list); + + op->dest.type = OP_DEST_REG; + op->dest.offset = 0; + op->dest.reg = rd; + + op->src.type = OP_SRC_AND; + op->src.offset = 0; + op->src.reg = rd; + + return 0; +} + int arm_decode_move_wide(u32 instr, enum insn_type *type, unsigned long *immediate, struct list_head *ops_list) { diff --git a/tools/objtool/arch/arm64/include/insn_decode.h b/tools/objtool/arch/arm64/include/insn_decode.h index 65e60b293a07..6f68e8887cdb 100644 --- a/tools/objtool/arch/arm64/include/insn_decode.h +++ b/tools/objtool/arch/arm64/include/insn_decode.h @@ -16,6 +16,7 @@ #define INSN_PCREL 0b001 //0b00x #define INSN_ADD_SUB 0b010 #define INSN_ADD_TAG 0b011 +#define INSN_LOGICAL 0b100 #define INSN_MOVE_WIDE 0b101 #define INSN_BITFIELD 0b110 #define INSN_EXTRACT 0b111 @@ -38,6 +39,8 @@ int arm_decode_add_sub(u32 instr, enum insn_type *type, int arm_decode_add_sub_tags(u32 instr, enum insn_type *type, unsigned long *immediate, struct list_head *ops_list); +int arm_decode_logical(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list); int arm_decode_move_wide(u32 instr, enum insn_type *type, unsigned long *immediate, struct list_head *ops_list); int arm_decode_bitfield(u32 instr, enum insn_type *type,