| Message ID | 20200123115852.55595-3-andrew.murray@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: perf: Add support for ARMv8.5-PMU 64-bit counters | expand |
On 2020-01-23 11:58, Andrew Murray wrote: > ARMv8.5-PMU introduces 64-bit event counters, however KVM doesn't yet > support this. Let's trap the Debug Feature Registers in order to limit > PMUVer/PerfMon in the Debug Feature Registers to PMUv3 for ARMv8.4. > > Signed-off-by: Andrew Murray <andrew.murray@arm.com> > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > arch/arm64/include/asm/sysreg.h | 5 +++++ > arch/arm64/kvm/sys_regs.c | 11 +++++++++++ > 2 files changed, 16 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h > b/arch/arm64/include/asm/sysreg.h > index 6e919fafb43d..d969df417f88 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -672,6 +672,11 @@ > #define ID_AA64DFR0_TRACEVER_SHIFT 4 > #define ID_AA64DFR0_DEBUGVER_SHIFT 0 > > +#define ID_DFR0_PERFMON_SHIFT 24 > + > +#define ID_DFR0_EL1_PMUVER_8_4 5 > +#define ID_AA64DFR0_EL1_PMUVER_8_4 5 > + > #define ID_ISAR5_RDM_SHIFT 24 > #define ID_ISAR5_CRC32_SHIFT 16 > #define ID_ISAR5_SHA2_SHIFT 12 > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 9f2165937f7d..028c93a88a51 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1085,6 +1085,17 @@ static u64 read_id_reg(const struct kvm_vcpu > *vcpu, > (0xfUL << ID_AA64ISAR1_API_SHIFT) | > (0xfUL << ID_AA64ISAR1_GPA_SHIFT) | > (0xfUL << ID_AA64ISAR1_GPI_SHIFT)); > + } else if (id == SYS_ID_AA64DFR0_EL1) { > + /* Limit guests to PMUv3 for ARMv8.4 */ > + val = cpuid_feature_cap_signed_field_width(val, > + ID_AA64DFR0_PMUVER_SHIFT, > + 4, ID_AA64DFR0_EL1_PMUVER_8_4); > + } else if (id == SYS_ID_DFR0_EL1) { > + /* Limit guests to PMUv3 for ARMv8.4 */ > + val = cpuid_feature_cap_signed_field_width(val, > + ID_DFR0_PERFMON_SHIFT, > + 4, ID_DFR0_EL1_PMUVER_8_4); I dont think this is right. Even today, we don't have support for PMMIR, so pretending we support v8.4 is not true (the guest will get an UNDEF). I would really stick to ARMv8.1 support here. You could post it as a fix, to be taken right away. M.
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 6e919fafb43d..d969df417f88 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -672,6 +672,11 @@ #define ID_AA64DFR0_TRACEVER_SHIFT 4 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 +#define ID_DFR0_PERFMON_SHIFT 24 + +#define ID_DFR0_EL1_PMUVER_8_4 5 +#define ID_AA64DFR0_EL1_PMUVER_8_4 5 + #define ID_ISAR5_RDM_SHIFT 24 #define ID_ISAR5_CRC32_SHIFT 16 #define ID_ISAR5_SHA2_SHIFT 12 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 9f2165937f7d..028c93a88a51 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1085,6 +1085,17 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, (0xfUL << ID_AA64ISAR1_API_SHIFT) | (0xfUL << ID_AA64ISAR1_GPA_SHIFT) | (0xfUL << ID_AA64ISAR1_GPI_SHIFT)); + } else if (id == SYS_ID_AA64DFR0_EL1) { + /* Limit guests to PMUv3 for ARMv8.4 */ + val = cpuid_feature_cap_signed_field_width(val, + ID_AA64DFR0_PMUVER_SHIFT, + 4, ID_AA64DFR0_EL1_PMUVER_8_4); + } else if (id == SYS_ID_DFR0_EL1) { + /* Limit guests to PMUv3 for ARMv8.4 */ + val = cpuid_feature_cap_signed_field_width(val, + ID_DFR0_PERFMON_SHIFT, + 4, ID_DFR0_EL1_PMUVER_8_4); + } return val;