| Message ID | 20200205143003.28408-11-martin.kepplinger@puri.sm (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: librem5-devkit: description updates | expand |
On Wed, Feb 05, 2020 at 03:30:01PM +0100, Martin Kepplinger wrote: > From: "Angus Ainslie (Purism)" <angus@akkea.ca> > > use vselect to set the io voltage to 1.8V > > Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca> > --- > arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts > index fbc7062c4633..8f920c554ebd 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts > @@ -789,6 +789,7 @@ > MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 > MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 > MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 > + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 How is the pin working without a pinctrl handle pointing it? Shawn > >; > }; > > @@ -800,6 +801,7 @@ > MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd > MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd > MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd > + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 > >; > }; > > @@ -811,6 +813,7 @@ > MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf > MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf > MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf > + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 > >; > }; > > -- > 2.20.1 >
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index fbc7062c4633..8f920c554ebd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -789,6 +789,7 @@ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 >; }; @@ -800,6 +801,7 @@ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 >; }; @@ -811,6 +813,7 @@ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 >; };