| Message ID | 20200205143003.28408-2-martin.kepplinger@puri.sm (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: librem5-devkit: description updates | expand |
On Wed, Feb 05, 2020 at 03:29:52PM +0100, Martin Kepplinger wrote: > From: "Angus Ainslie (Purism)" <angus@akkea.ca> > > Add missing sai2 and sai6 audio interface pinctrl definitions for the > Librem 5 devkit. > > Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca> > --- > .../dts/freescale/imx8mq-librem5-devkit.dts | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts > index 764a4cb4e125..9702db69d3ed 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts > @@ -555,6 +555,25 @@ > >; > }; > > + pinctrl_sai2: sai2grp { > + fsl,pins = < > + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 Please be consistent with existing indentation style. Shawn > + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 > + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 > + MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 > + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 > + >; > + }; > + > + pinctrl_sai6: sai6grp { > + fsl,pins = < > + MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 > + MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 > + MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 > + MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 > + >; > + }; > + > pinctrl_typec: typecgrp { > fsl,pins = < > MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16 > -- > 2.20.1 >
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 764a4cb4e125..9702db69d3ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -555,6 +555,25 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + >; + }; + + pinctrl_sai6: sai6grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 + >; + }; + pinctrl_typec: typecgrp { fsl,pins = < MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16