| Message ID | 20200210170656.82265-4-jernej.skrabec@siol.net (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | fc7c2bfb08c36d26b9cad391636566fcdb75fef0 |
| Headers | show |
| Series | arm64: dts: allwinner: a64: Enable deinterlace core | expand |
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 862b47dc9dc9..251c91724de1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1061,6 +1061,14 @@ pwm: pwm@1c21400 { status = "disabled"; }; + mbus: dram-controller@1c62000 { + compatible = "allwinner,sun50i-a64-mbus"; + reg = <0x01c62000 0x1000>; + clocks = <&ccu 112>; + dma-ranges = <0x00000000 0x40000000 0xc0000000>; + #interconnect-cells = <1>; + }; + csi: csi@1cb0000 { compatible = "allwinner,sun50i-a64-csi"; reg = <0x01cb0000 0x1000>;
A64 contains MBUS, which is the bus used by DMA devices to access system memory. MBUS controller is responsible for arbitration between channels based on set priority and can do some other things as well, like report bandwidth used. It also maps RAM region to different address than CPU. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)