diff mbox series

[2/7] clk: sunxi-ng: sun8i-de2: Split out H5 definitions

Message ID 20200210222807.206426-3-jernej.skrabec@siol.net (mailing list archive)
State New, archived
Headers show
Series clk: sunxi-ng: sun8i-de2: Multiple fixes | expand

Commit Message

Jernej Škrabec Feb. 10, 2020, 10:28 p.m. UTC 
H5 has less clocks and resets than A64. Currently that's not obvious
because A64 is missing rotation core related clocks and reset.

Split out H5 definition. A64 structures will be fixed in subsequent
commit.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

Comments

Chen-Yu Tsai Feb. 11, 2020, 7:36 a.m. UTC | #1 
On Tue, Feb 11, 2020 at 6:28 AM Jernej Skrabec <jernej.skrabec@siol.net> wrote:
>
> H5 has less clocks and resets than A64. Currently that's not obvious
> because A64 is missing rotation core related clocks and reset.
>
> Split out H5 definition. A64 structures will be fixed in subsequent
> commit.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>

Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU")

You should also note that this patch requires commit 19368d99746e
("clk: sunxi-ng: add support for Allwinner H3 DE2 CCU") for the
H3 clock list.

Code wise everything looks in order.

ChenYu
diff mbox series

Patch

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index a928e0c32222..f449c22e59e8 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -192,6 +192,12 @@  static struct ccu_reset_map sun50i_a64_de2_resets[] = {
 	[RST_WB]	= { 0x08, BIT(2) },
 };
 
+static struct ccu_reset_map sun50i_h5_de2_resets[] = {
+	[RST_MIXER0]	= { 0x08, BIT(0) },
+	[RST_MIXER1]	= { 0x08, BIT(1) },
+	[RST_WB]	= { 0x08, BIT(2) },
+};
+
 static struct ccu_reset_map sun50i_h6_de3_resets[] = {
 	[RST_MIXER0]	= { 0x08, BIT(0) },
 	[RST_MIXER1]	= { 0x08, BIT(1) },
@@ -239,6 +245,16 @@  static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
 	.num_resets	= ARRAY_SIZE(sun50i_a64_de2_resets),
 };
 
+static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
+	.ccu_clks	= sun8i_h3_de2_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_de2_clks),
+
+	.hw_clks	= &sun8i_h3_de2_hw_clks,
+
+	.resets		= sun50i_h5_de2_resets,
+	.num_resets	= ARRAY_SIZE(sun50i_h5_de2_resets),
+};
+
 static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {
 	.ccu_clks	= sun50i_h6_de3_clks,
 	.num_ccu_clks	= ARRAY_SIZE(sun50i_h6_de3_clks),
@@ -347,7 +363,7 @@  static const struct of_device_id sunxi_de2_clk_ids[] = {
 	},
 	{
 		.compatible = "allwinner,sun50i-h5-de2-clk",
-		.data = &sun50i_a64_de2_clk_desc,
+		.data = &sun50i_h5_de2_clk_desc,
 	},
 	{
 		.compatible = "allwinner,sun50i-h6-de3-clk",