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Received: from DB7PR04MB4618.eurprd04.prod.outlook.com (52.135.139.151) by DB7PR04MB4010.eurprd04.prod.outlook.com (52.135.128.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2750.22; Tue, 25 Feb 2020 12:59:33 +0000 Received: from DB7PR04MB4618.eurprd04.prod.outlook.com ([fe80::5cb4:81c8:1618:5ca]) by DB7PR04MB4618.eurprd04.prod.outlook.com ([fe80::5cb4:81c8:1618:5ca%7]) with mapi id 15.20.2750.021; Tue, 25 Feb 2020 12:59:33 +0000 From: Joakim Zhang To: will@kernel.org, mark.rutland@arm.com, robin.murphy@arm.com Subject: [PATCH 1/2] perf/imx_ddr: Correct the CLEAR bit definition Date: Tue, 25 Feb 2020 20:56:43 +0800 Message-Id: <20200225125644.18853-1-qiangqing.zhang@nxp.com> X-Mailer: git-send-email 2.17.1 X-ClientProxiedBy: SG2PR06CA0186.apcprd06.prod.outlook.com (2603:1096:4:1::18) To DB7PR04MB4618.eurprd04.prod.outlook.com (2603:10a6:5:38::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.71) by SG2PR06CA0186.apcprd06.prod.outlook.com (2603:1096:4:1::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2750.18 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: zx72QxmGI3ToUyid1pobF454tNHbmj7nGE10C1+U3tjsvj9oIuFAY5S4wefg71nowKfsn1bnlaigRNWBbkdvksjI56rsgUZUE35apjeTk9R3xySlXZ0wUqnSwSCsYSR5mrvKhNXIm9HeM05N7ZDsdK5f8LF9FgO9TeqTxxRMoDpHXQq/3/dzFyesj966ZmrB8B0ldeBeptWkMp+xesQstMMCe/uxvbq1lHQsHJ58bRZeLfN/KXafVNTbXOrfpjsWcOByLnx2sMa+vA8mzTQAwvBsAimaupgAXJaNNL7pscmmlagAPQLAGoO6BSthYO0dNwzHBm8/ZQI/bq4UXvBpEsqmEXvZLtNitKje47WvjmNJr7haQSE4Z5W6CM4U2TpUQ/MeT9pG7uaEUmm/i6g2BIjNe9Aa0AMrPqk7ZNB3KgBoPShWtfpq3tOKYiUo05Tj0ikwPFu0V2AXvFps4QVhL/b7ChDw+CA1T1jbq2pLFWuCVfBxZU+jahnX7jQToiHTQXRmqGxQ/kFvU1b7zXf6QPafktYZy6vYNYMUezuduFc= X-MS-Exchange-AntiSpam-MessageData: H00tBEMa+Q4QxJ9woCgvwRD4EojqHmJvqGwXt8SyZDAV6aT3bzwMIk6TYzW1KHLlJI7edVnnzPRnyzMnyluzAC5PFOwXvQAlBe69k0qZp6vBSIYePfma8VNl9tYilQsN2JSrZABs2RvEGrrRyggmKg== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 50e62a12-6354-47f0-7b93-08d7b9f28f0b X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Feb 2020 12:59:33.2331 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: O2FaUq+vb6EXiys+Frj8D3KPeWpHwZw20v256IIcUKog7qHJStZu4R3t27H4fDoxE5x4+benzvxt64hHdEdHsQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB4010 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200225_045945_404892_C0BE53DE X-CRM114-Status: GOOD ( 11.94 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.13.78 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 MSGID_FROM_MTA_HEADER Message-Id was added by a relay X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org ddr_perf_event_stop will firstly call ddr_perf_counter_enable to disable the counter, and then call ddr_perf_event_update to read the counter value. When disable the counter, it will write 0 into COUNTER_CNTL[CLEAR] bit which cause the counter value cleared. Counter value will always be 0 when update the counter. The correct definition of CLEAR bit is that write 0 to clear the counter value. Signed-off-by: Joakim Zhang --- drivers/perf/fsl_imx8_ddr_perf.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 95dca2cb5265..90884d14f95f 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -388,9 +388,10 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, if (enable) { /* - * must disable first, then enable again - * otherwise, cycle counter will not work - * if previous state is enabled. + * cycle counter is special which should firstly write 0 then + * write 1 into CLEAR bit to clear it. Other counters only + * need write 0 into CLEAR bit and it turns out to be 1 by + * hardware. Below enable flow is harmless for all counters. */ writel(0, pmu->base + reg); val = CNTL_EN | CNTL_CLEAR; @@ -398,7 +399,8 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, writel(val, pmu->base + reg); } else { /* Disable counter */ - writel(0, pmu->base + reg); + val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; + writel(val, pmu->base + reg); } }