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X-Microsoft-Antispam-Message-Info: q/ulAJ3Fdr6f+GbC4bSBoXFliQooJDT2xVYvfFI8TZ5VknNujyi/be9xd53CukZaTvLTR7pp7eiDkLbv/Y3ge0h1VFjfJjeVJUvxx+qj2vpTutpN+f5S6zH6mW7dDA2/ETrSYawG9oDveAbFbR1r6JHsfyZpzKwDbTRo7KkuC834eJQB3UHCK37S6IL8lhQhpHLdrR8Dia/xABW8eiV9gDdwWI7pQgL62xnxt0lJhTWiTcfqhjuTjPebAe6pJqxINDLWQcr0ouLje+aIjADfrD0anlhYqbTbZF2VjlF7eYiyyTQY3J7nazZsa6t/RWZeLrrF8h1i/Z8Wc7k2uZZPftN5A5qBWlY1DTHjCyN7bhBumffn3JE173zUzEFmjTgoAQwgNK/U4SEBhwAis+w9dut2qYAXSMMX63I7Fktu095riwadkel0J+ltN02S0uKsl6Q4iBTOS9dlv4skgE3+eqs9eS02SSeoWFM2svCcPxX60NtZDRwHsmZ3jQ3XiHxVf+PWhdyJV6RRXVp3B1id+GDd2boygWt5bpxiXewtiWU= X-MS-Exchange-AntiSpam-MessageData: iy9Lzrkiw0kj0jS9mRxFPtkWDhJ698RG7JNsf865LY/oPIXLi07TfnSRcQBdXggrIHwb16Wlhrbe4G4kAX2DwAFkmz0c53a8RHkKgB8TAr8iSy2WDC5eeDnM8HBAvWlK0f6/saAhWI6sbPDvIdh1yw== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9b0a49e4-ca69-4e9d-3938-08d7b9f29073 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Feb 2020 12:59:35.4977 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YYMsKO+3revKbgOfs8yQjz/Nq22dQu6I+c8H5LEz0fZ8lrIDkAvl77j4704Uuy97egDolcySAdQrvXCWVkIOpQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB4010 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200225_045948_800685_1BA5342D X-CRM114-Status: GOOD ( 16.36 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.13.78 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 MSGID_FROM_MTA_HEADER Message-Id was added by a relay X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DDR perf driver now only supports free-running event counters (counter1/2/3), which means that event counters will continue counting even they are overflow. However, the situation is changed on i.MX8MP, event counters are not free-running any more. Event counters would stop counting if they are overflow. So we need clear event counters when cycle counter overflow. The patch adds stop counter support which would be compatible to free-running counter. Signed-off-by: Joakim Zhang --- drivers/perf/fsl_imx8_ddr_perf.c | 37 ++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 90884d14f95f..5713f0631f79 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #define COUNTER_CNTL 0x0 @@ -82,6 +83,7 @@ struct ddr_pmu { const struct fsl_ddr_devtype_data *devtype_data; int irq; int id; + spinlock_t lock; }; enum ddr_perf_filter_capabilities { @@ -368,16 +370,19 @@ static void ddr_perf_event_update(struct perf_event *event) struct hw_perf_event *hwc = &event->hw; u64 delta, prev_raw_count, new_raw_count; int counter = hwc->idx; + unsigned long flags; - do { - prev_raw_count = local64_read(&hwc->prev_count); - new_raw_count = ddr_perf_read_counter(pmu, counter); - } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, - new_raw_count) != prev_raw_count); + spin_lock_irqsave(&pmu->lock, flags); + + prev_raw_count = local64_read(&hwc->prev_count); + new_raw_count = ddr_perf_read_counter(pmu, counter); delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF; local64_add(delta, &event->count); + local64_set(&hwc->prev_count, new_raw_count); + + spin_unlock_irqrestore(&pmu->lock, flags); } static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, @@ -546,7 +551,7 @@ static irqreturn_t ddr_perf_irq_handler(int irq, void *p) /* * When the cycle counter overflows, all counters are stopped, * and an IRQ is raised. If any other counter overflows, it - * continues counting, and no IRQ is raised. + * stop counting, and no IRQ is raised. * * Cycles occur at least 4 times as often as other events, so we * can update all events on a cycle counter overflow and not @@ -566,6 +571,25 @@ static irqreturn_t ddr_perf_irq_handler(int irq, void *p) cycle_event = event; } + spin_lock(&pmu->lock); + + for (i = 0; i < NUM_COUNTERS; i++) { + if (!pmu->events[i]) + continue; + + event = pmu->events[i]; + + if (event->hw.idx == EVENT_CYCLES_COUNTER) + continue; + + /* clear non-cycle counters */ + ddr_perf_counter_enable(pmu, event->attr.config, event->hw.idx, true); + + local64_set(&event->hw.prev_count, 0); + } + + spin_unlock(&pmu->lock); + ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID, EVENT_CYCLES_COUNTER, @@ -619,6 +643,7 @@ static int ddr_perf_probe(struct platform_device *pdev) num = ddr_perf_init(pmu, base, &pdev->dev); platform_set_drvdata(pdev, pmu); + spin_lock_init(&pmu->lock); name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", num);