| Message ID | 20200227123726.12910-1-yamada.masahiro@socionext.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | bc350d1073bc4d1147697a68fac68e062dd9912f |
| Headers | show |
| Series | ARM: dts: uniphier: rename cache controller nodes to follow json-schema | expand |
On Thu, Feb 27, 2020 at 9:38 PM Masahiro Yamada <yamada.masahiro@socionext.com> wrote: > > Follow the standard nodename pattern > "^(cache-controller|cpu)(@[0-9a-f,]+)*$" defined in > schemas/cache-controller.yaml of dt-schema. > > Otherwise, after the dt-binding is converted to json-schema, > 'make ARCH=arm dtbs_check' will show a warning like this: > > l2-cache@500c0000: $nodename:0: 'l2-cache@500c0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' > > Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> > --- Applied to linux-uniphier. > > arch/arm/boot/dts/uniphier-ld4.dtsi | 2 +- > arch/arm/boot/dts/uniphier-pro4.dtsi | 2 +- > arch/arm/boot/dts/uniphier-pro5.dtsi | 4 ++-- > arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +- > arch/arm/boot/dts/uniphier-sld8.dtsi | 2 +- > 5 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi > index 197bee7d8b7f..06e7400d2940 100644 > --- a/arch/arm/boot/dts/uniphier-ld4.dtsi > +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi > @@ -51,7 +51,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, > <0x506c0000 0x400>; > diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi > index b02bc8a6346b..1c866f0306fc 100644 > --- a/arch/arm/boot/dts/uniphier-pro4.dtsi > +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi > @@ -59,7 +59,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, > <0x506c0000 0x400>; > diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi > index f84a43a10f38..da772429b55a 100644 > --- a/arch/arm/boot/dts/uniphier-pro5.dtsi > +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi > @@ -131,7 +131,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, > <0x506c0000 0x400>; > @@ -144,7 +144,7 @@ > next-level-cache = <&l3>; > }; > > - l3: l3-cache@500c8000 { > + l3: cache-controller@500c8000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, > <0x506c8000 0x400>; > diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi > index 989b2a241822..7044f8700cb2 100644 > --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi > +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi > @@ -157,7 +157,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, > <0x506c0000 0x400>; > diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi > index fbfd25050a04..09992163e1f4 100644 > --- a/arch/arm/boot/dts/uniphier-sld8.dtsi > +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi > @@ -51,7 +51,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, > <0x506c0000 0x400>; > -- > 2.17.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 197bee7d8b7f..06e7400d2940 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -51,7 +51,7 @@ ranges; interrupt-parent = <&intc>; - l2: l2-cache@500c0000 { + l2: cache-controller@500c0000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index b02bc8a6346b..1c866f0306fc 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -59,7 +59,7 @@ ranges; interrupt-parent = <&intc>; - l2: l2-cache@500c0000 { + l2: cache-controller@500c0000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index f84a43a10f38..da772429b55a 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -131,7 +131,7 @@ ranges; interrupt-parent = <&intc>; - l2: l2-cache@500c0000 { + l2: cache-controller@500c0000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; @@ -144,7 +144,7 @@ next-level-cache = <&l3>; }; - l3: l3-cache@500c8000 { + l3: cache-controller@500c8000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 989b2a241822..7044f8700cb2 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -157,7 +157,7 @@ ranges; interrupt-parent = <&intc>; - l2: l2-cache@500c0000 { + l2: cache-controller@500c0000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index fbfd25050a04..09992163e1f4 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -51,7 +51,7 @@ ranges; interrupt-parent = <&intc>; - l2: l2-cache@500c0000 { + l2: cache-controller@500c0000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
Follow the standard nodename pattern "^(cache-controller|cpu)(@[0-9a-f,]+)*$" defined in schemas/cache-controller.yaml of dt-schema. Otherwise, after the dt-binding is converted to json-schema, 'make ARCH=arm dtbs_check' will show a warning like this: l2-cache@500c0000: $nodename:0: 'l2-cache@500c0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> --- arch/arm/boot/dts/uniphier-ld4.dtsi | 2 +- arch/arm/boot/dts/uniphier-pro4.dtsi | 2 +- arch/arm/boot/dts/uniphier-pro5.dtsi | 4 ++-- arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +- arch/arm/boot/dts/uniphier-sld8.dtsi | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-)