From patchwork Mon Mar 9 16:17:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 11427553 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E60171800 for ; Mon, 9 Mar 2020 16:21:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B868920578 for ; Mon, 9 Mar 2020 16:21:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="O8KNkFPd"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="UhaoL7kC" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B868920578 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NxuXVzaw0jKnNTmTwjEwyHXBz+IvvxHHpkKFPWMov4g=; b=O8KNkFPd8waE4Z c8xUi62DFuJvd+SvX5binQ6IyJ4BPmHSmdrQPrOp/WwKM3pomvig9s3WdSOKIr7BOVSPS4LVB05h7 YuMNUkLEhR9+vr56jujKTk6v0j8yYCByz56TCkSprYp4EBK4khBN6DS7X0kQ3azA+6aj1gjj4MPyA KhEgUbZfc7khkMdfbbbopfnmTgqAgZufuOdMG/9GV+vJg3dJDo/0Sp1TkQWTkKy4x0lfJKE9HyAPN xZ0bLA6w0a7zPY6u+lM3HAKALMCZ237F9DoLMDzOcrKD14mgdaSvwq1mz39mWVjNbUso7Rz1qmUHC /AeXUXify9olHcljMv0g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jBL9m-0003yb-Mv; Mon, 09 Mar 2020 16:21:30 +0000 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jBL6P-00009e-Gr for linux-arm-kernel@lists.infradead.org; Mon, 09 Mar 2020 16:18:05 +0000 Received: by mail-pl1-x636.google.com with SMTP id g12so4175455plo.3 for ; Mon, 09 Mar 2020 09:18:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RsBGS2ZyIR5T7Vv9mrAyI7pDtD/V4EuVkA+MmJQJE2g=; b=UhaoL7kCT2p7pyWYBJrsrOvYMO+JkWuA7yasgLozscr8tzFdEmVp6Q0BhX1k36GBxg 6e5ihZtTw8Iz/ZFgI4QIpW8ut1hhPEab8ubVHTzVkA5p3P0jofClFhFNvchPi78rpxFV +DiWhpAEIEF2ncHvLQeMI1D7BAVuciFLx6Q4Jl48RRya6lr5awSwFaiR2B/RFVLW4Jcn /+EF4SzFwXcDxo2TKftvfZeAstEIzgnc2L+VkTqKfY8r1R7wWnXZgwzfEIkkuzYtzkZU o8Uo1IxYGEj31rqmD7xlwUzzdljEH0+g+LVJ15RYQSwVGL7rIT2soc0cmCpqbBSLHdXN j3AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RsBGS2ZyIR5T7Vv9mrAyI7pDtD/V4EuVkA+MmJQJE2g=; b=LDEbjl4gAbKaCNiN0WKg/1uyRAApTKhNczcMn7HrbyMVP+JdVgNXoqx4LmE2i1RpSl 2oan8aA2+xLO4zQVncgD83jDonllXSMJ3EbhsJEib4TRE7MO2JbD2x2ajI+9ItWg026o uENAypsi/Oc9utmlcTtfIsQlW+Rn9qMEAfjv9xdAFqQkQtzWazxWbCiwWixKtwG+FQmD fWOr3FP0VCwhUWL1E7cGNjyUkZRfmdi4ByRNhvzoUkYo94FYK+GzCZ4vpdarEgqR7CUt FD44mC5QB6qrqlV5qY2FdmjBdNSpwgjgy4+dY67fhXj5dRw5NQZaYAmalGRxsoM5gDtU DKrQ== X-Gm-Message-State: ANhLgQ1KtIzpuQP5QO7lg7CYxP8YUCe1qZWyU6+xUHkJApxUqujTKm1t +XRVTuiqjWSesmiUGDDKo0qsgg== X-Google-Smtp-Source: ADFU+vsj+SZPV9vtK/8GNfO02y4i5QVjETMu3l7AuSlRDPJf0D6fRsOPTqzLS3+HeoRDZnhLZGGysQ== X-Received: by 2002:a17:902:7d94:: with SMTP id a20mr2065772plm.307.1583770680324; Mon, 09 Mar 2020 09:18:00 -0700 (PDT) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id m11sm38403pjl.18.2020.03.09.09.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2020 09:17:59 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 10/13] docs: coresight: Update documentation for CoreSight to cover CTI Date: Mon, 9 Mar 2020 10:17:45 -0600 Message-Id: <20200309161748.31975-11-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200309161748.31975-1-mathieu.poirier@linaro.org> References: <20200309161748.31975-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200309_091801_591426_F4C87424 X-CRM114-Status: GOOD ( 22.85 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:636 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Mike Leach Add new document covering CTI / CTM usage in CoreSight. Add section in coresight.rst introducing CTI and CTM modules with link to new document. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Reviewed-by: Mathieu Poirier Reviewed-by: Randy Dunlap Signed-off-by: Mathieu Poirier --- .../trace/coresight/coresight-ect.rst | 211 ++++++++++++++++++ Documentation/trace/coresight/coresight.rst | 13 ++ 2 files changed, 224 insertions(+) create mode 100644 Documentation/trace/coresight/coresight-ect.rst diff --git a/Documentation/trace/coresight/coresight-ect.rst b/Documentation/trace/coresight/coresight-ect.rst new file mode 100644 index 000000000000..067cee91c857 --- /dev/null +++ b/Documentation/trace/coresight/coresight-ect.rst @@ -0,0 +1,211 @@ +============================================= +CoreSight Embedded Cross Trigger (CTI & CTM). +============================================= + + :Author: Mike Leach + :Date: November 2019 + +Hardware Description +-------------------- + +The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes +individual input and output hardware signals known as triggers to and from +devices and interconnects them via the Cross Trigger Matrix (CTM) to other +devices via numbered channels, in order to propagate events between devices. + +e.g.:: + + 0000000 in_trigs ::::::: + 0 C 0----------->: : +======>(other CTI channel IO) + 0 P 0<-----------: : v + 0 U 0 out_trigs : : Channels ***** ::::::: + 0000000 : CTI :<=========>*CTM*<====>: CTI :---+ + ####### in_trigs : : (id 0-3) ***** ::::::: v + # ETM #----------->: : ^ ####### + # #<-----------: : +---# ETR # + ####### out_trigs ::::::: ####### + +The CTI driver enables the programming of the CTI to attach triggers to +channels. When an input trigger becomes active, the attached channel will +become active. Any output trigger attached to that channel will also +become active. The active channel is propagated to other CTIs via the CTM, +activating connected output triggers there, unless filtered by the CTI +channel gate. + +It is also possible to activate a channel using system software directly +programming registers in the CTI. + +The CTIs are registered by the system to be associated with CPUs and/or other +CoreSight devices on the trace data path. When these devices are enabled the +attached CTIs will also be enabled. By default/on power up the CTIs have +no programmed trigger/channel attachments, so will not affect the system +until explicitly programmed. + +The hardware trigger connections between CTIs and devices is implementation +defined, unless the CPU/ETM combination is a v8 architecture, in which case +the connections have an architecturally defined standard layout. + +The hardware trigger signals can also be connected to non-CoreSight devices +(e.g. UART), or be propagated off chip as hardware IO lines. + +All the CTI devices are associated with a CTM. On many systems there will be a +single effective CTM (one CTM, or multiple CTMs all interconnected), but it is +possible that systems can have nets of CTIs+CTM that are not interconnected by +a CTM to each other. On these systems a CTM index is declared to associate +CTI devices that are interconnected via a given CTM. + +Sysfs files and directories +--------------------------- + +The CTI devices appear on the existing CoreSight bus alongside the other +CoreSight devices:: + + >$ ls /sys/bus/coresight/devices + cti_cpu0 cti_cpu2 cti_sys0 etm0 etm2 funnel0 replicator0 tmc_etr0 + cti_cpu1 cti_cpu3 cti_sys1 etm1 etm3 funnel1 tmc_etf0 tpiu0 + +The ``cti_cpu`` named CTIs are associated with a CPU, and any ETM used by +that core. The ``cti_sys`` CTIs are general system infrastructure CTIs that +can be associated with other CoreSight devices, or other system hardware +capable of generating or using trigger signals.:: + + >$ ls /sys/bus/coresight/devices/etm0/cti_cpu0 + channels ctmid enable nr_trigger_cons mgmt power regs subsystem + triggers0 triggers1 uevent + +*Key file items are:-* + * ``enable``: enables/disables the CTI. + * ``ctmid`` : associated CTM - only relevant if system has multiple CTI+CTM + clusters that are not interconnected. + * ``nr_trigger_cons`` : total connections - triggers directories. + +*Sub-directories:-* + * ``triggers``: contains list of triggers for an individual connection. + * ``channels``: Contains the channel API - CTI main programming interface. + * ``regs``: Gives access to the raw programmable CTI regs. + * ``mgmt``: the standard CoreSight management registers. + + +triggers directories +~~~~~~~~~~~~~~~~~~~~~~~ + +Individual trigger connection information. This describes trigger signals for +CoreSight and non-CoreSight connections. + +Each triggers directory has a set of parameters describing the triggers for +the connection. + + * ``name`` : name of connection + * ``in_signals`` : input trigger signal indexes used in this connection. + * ``in_types`` : functional types for in signals. + * ``out_signals`` : output trigger signals for this connection. + * ``out_types`` : functional types for out signals. + +e.g:: + + >$ ls ./cti_cpu0/triggers0/ + in_signals in_types name out_signals out_types + >$ cat ./cti_cpu0/triggers0/name + cpu0 + >$ cat ./cti_cpu0/triggers0/out_signals + 0-2 + >$ cat ./cti_cpu0/triggers0/out_types + pe_edbgreq pe_dbgrestart pe_ctiirq + >$ cat ./cti_cpu0/triggers0/in_signals + 0-1 + >$ cat ./cti_cpu0/triggers0/in_types + pe_dbgtrigger pe_pmuirq + +If a connection has zero signals in either the 'in' or 'out' triggers then +those parameters will be omitted. + +Channels API Directory +~~~~~~~~~~~~~~~~~~~~~~ + +This provides an easy way to attach triggers to channels, without needing +the multiple register operations that are required if manipulating the +'regs' sub-directory elements directly. + +A number of files provide this API:: + + >$ ls ./cti_sys0/channels/ + chan_clear chan_inuse chan_xtrigs_view trigin_detach + chan_free chan_pulse chan_xtrigs_view_sel trigout_attach + chan_gate_disable chan_set trig_filter_enable trigout_detach + chan_gate_enable chan_xtrigs_reset trigin_attach trigout_filtered + +Most access to these elements take the form:: + + echo [] > // + +where the optional is only needed for trigXX_attach | detach +operations. + +e.g.:: + + >$ echo 0 1 > ./cti_sys0/channels/trigout_attach + >$ echo 0 > ./cti_sys0/channels/chan_set + +Attaches trigout(1) to channel(0), then activates channel(0) generating a +set state on cti_sys0.trigout(1) + + +*API operations* + + * ``trigin_attach, trigout_attach``: Attach a channel to a trigger signal. + * ``trigin_detach, trigout_detach``: Detach a channel from a trigger signal. + * ``chan_set``: Set the channel - the set state will be propagated around + the CTM to other connected devices. + * ``chan_clear``: Clear the channel. + * ``chan_pulse``: Set the channel for a single CoreSight clock cycle. + * ``chan_gate_enable``: Write operation sets the CTI gate to propagate + (enable) the channel to other devices. This operation takes a channel + number. CTI gate is enabled for all channels by default at power up. Read + to list the currently enabled channels on the gate. + * ``chan_gate_disable``: Write channel number to disable gate for that + channel. + * ``chan_inuse``: Show the current channels attached to any signal + * ``chan_free``: Show channels with no attached signals. + * ``chan_xtrig_view``: write a channel number to select a channel to view, + read to show the cross triggers programmed for the selected channel. + * ``trig_filter_enable``: Defaults to enabled, disable to allow potentially + dangerous output signals to be set. + * ``trigout_filtered``: Trigger out signals that are prevented from being + set if filtering ``trig_filter_enable`` is enabled. One use is to prevent + accidental ``EDBGREQ`` signals stopping a core. + * ``chan_xtrigs_reset``: Write 1 to clear all channel / trigger programming. + Resets device hardware to default state. + + +The example below attaches input trigger index 1 to channel 2, and output +trigger index 6 to the same channel. It then examines the state of the +channel / trigger connections using the appropriate sysfs attributes. + +The settings mean that if either input trigger 1, or channel 2 go active then +trigger out 6 will go active. We then enable the CTI, and use the software +channel control to activate channel 2. We see the active channel on the +``choutstatus`` register and the active signal on the ``trigoutstatus`` +register. Finally clearing the channel removes this. + +e.g.:: + + .../cti_sys0/channels# echo 2 1 > trigin_attach + .../cti_sys0/channels# echo 2 6 > trigout_attach + .../cti_sys0/channels# cat chan_free + 0-1,3 + .../cti_sys0/channels# cat chan_inuse + 2 + .../cti_sys0/channels# echo 2 > chan_xtrigs_view + .../cti_sys0/channels# cat chan_xtrigs_view + [2] IN: 1 OUT: 6 + .../cti_sys0/# echo 1 > enable + .../cti_sys0/channels# echo 2 > chan_set + .../cti_sys0/channels# cat ../regs/choutstatus + 0x4 + .../cti_sys0/channels# cat ../regs/trigoutstatus + 0x40 + .../cti_sys0/channels# echo 2 > chan_clear + .../cti_sys0/channels# cat ../regs/trigoutstatus + 0x0 + .../cti_sys0/channels# cat ../regs/choutstatus + 0x0 diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst index a566719f8e7e..108600ee1e12 100644 --- a/Documentation/trace/coresight/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -491,8 +491,21 @@ interface provided for that purpose by the generic STM API:: Details on how to use the generic STM API can be found here:- :doc:`../stm` [#second]_. +The CTI & CTM Modules +--------------------- + +The CTI (Cross Trigger Interface) provides a set of trigger signals between +individual CTIs and components, and can propagate these between all CTIs via +channels on the CTM (Cross Trigger Matrix). + +A separate documentation file is provided to explain the use of these devices. +(:doc:`coresight-ect`) [#fourth]_. + + .. [#first] Documentation/ABI/testing/sysfs-bus-coresight-devices-stm .. [#second] Documentation/trace/stm.rst .. [#third] https://github.com/Linaro/perf-opencsd + +.. [#fourth] Documentation/trace/coresight/coresight-ect.rst