From patchwork Tue Mar 17 12:22:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincenzo Frascino X-Patchwork-Id: 11442805 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF1351667 for ; Tue, 17 Mar 2020 12:29:07 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B153A2073E for ; Tue, 17 Mar 2020 12:29:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="hVE1Rgxv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B153A2073E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DgkJyncmM45BBJcW3/xSEfygTT9y7jz8ZAgdlmAZm9E=; b=hVE1Rgxvsm6Avg 0MwFiMO8G+4QG2vxA9+a2XJoyGrHTd+4gLjXUmk95vbcOgSTRjEUw8mwUn1j31BqZsD/8KJ5r0zUJ uwltZyeNAQGmEYVNP+F/nCW3jXB/KWvZjXqa0GBKjCcdVEgu88IbuxC0bnKj5GXGdNGB3LJkObbrT Ch0R7QOXKJiPl02guvetFRnfSWCLVZWnSRUJ1mC27t43G7ERXOLEl8ph60SeDKrsphSaOnBjTGgwh vHnWNEHGkYtEs8hTvaBZR15w3EAn+QUiRo0g6q0ifE3wzv8vyEZJ3W3+wrylDziqJeiBVS/JfEmhi OnqAxlzlogawjTld1xCg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jEBLD-0004XE-7K; Tue, 17 Mar 2020 12:29:03 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jEBGN-0006cK-3R for linux-arm-kernel@lists.infradead.org; Tue, 17 Mar 2020 12:24:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 96E4530E; Tue, 17 Mar 2020 05:24:02 -0700 (PDT) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 86AAD3F534; Tue, 17 Mar 2020 05:23:59 -0700 (PDT) From: Vincenzo Frascino To: linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, clang-built-linux@googlegroups.com, linux-mips@vger.kernel.org, x86@kernel.org Subject: [PATCH v4 22/26] mips: vdso: Enable mips to use common headers Date: Tue, 17 Mar 2020 12:22:16 +0000 Message-Id: <20200317122220.30393-23-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200317122220.30393-1-vincenzo.frascino@arm.com> References: <20200317122220.30393-1-vincenzo.frascino@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200317_052403_270431_419BEA55 X-CRM114-Status: GOOD ( 14.52 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Nick Desaulniers , Dmitry Safonov <0x7f454c46@gmail.com>, Kees Cook , Arnd Bergmann , Stephen Boyd , Catalin Marinas , Paul Burton , Will Deacon , Russell King , Mark Salyzyn , Paul Burton , Ingo Molnar , Borislav Petkov , Andy Lutomirski , Marc Zyngier , Thomas Gleixner , Vincenzo Frascino , Peter Collingbourne , Andrei Vagin Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Enable mips to use only the common headers in the implementation of the vDSO library. Cc: Paul Burton Signed-off-by: Vincenzo Frascino --- arch/mips/include/asm/processor.h | 16 +------------- arch/mips/include/asm/vdso/gettimeofday.h | 4 ---- arch/mips/include/asm/vdso/processor.h | 27 +++++++++++++++++++++++ 3 files changed, 28 insertions(+), 19 deletions(-) create mode 100644 arch/mips/include/asm/vdso/processor.h diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 7619ad319400..4c9cc667f3ed 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -22,6 +22,7 @@ #include #include #include +#include /* * System setup and hardware flags.. @@ -385,21 +386,6 @@ unsigned long get_wchan(struct task_struct *p); #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29]) #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status) -#ifdef CONFIG_CPU_LOONGSON64 -/* - * Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a - * tight read loop is executed, because reads take priority over writes & the - * hardware (incorrectly) doesn't ensure that writes will eventually occur. - * - * Since spin loops of any kind should have a cpu_relax() in them, force an SFB - * flush from cpu_relax() such that any pending writes will become visible as - * expected. - */ -#define cpu_relax() smp_mb() -#else -#define cpu_relax() barrier() -#endif - /* * Return_address is a replacement for __builtin_return_address(count) * which on certain architectures cannot reasonably be implemented in GCC diff --git a/arch/mips/include/asm/vdso/gettimeofday.h b/arch/mips/include/asm/vdso/gettimeofday.h index 88c3de1bdf22..c63ddcaea54c 100644 --- a/arch/mips/include/asm/vdso/gettimeofday.h +++ b/arch/mips/include/asm/vdso/gettimeofday.h @@ -13,12 +13,8 @@ #ifndef __ASSEMBLY__ -#include -#include - #include #include -#include #include #include diff --git a/arch/mips/include/asm/vdso/processor.h b/arch/mips/include/asm/vdso/processor.h new file mode 100644 index 000000000000..511c95d735e6 --- /dev/null +++ b/arch/mips/include/asm/vdso/processor.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 ARM Ltd. + */ +#ifndef __ASM_VDSO_PROCESSOR_H +#define __ASM_VDSO_PROCESSOR_H + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_CPU_LOONGSON64 +/* + * Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a + * tight read loop is executed, because reads take priority over writes & the + * hardware (incorrectly) doesn't ensure that writes will eventually occur. + * + * Since spin loops of any kind should have a cpu_relax() in them, force an SFB + * flush from cpu_relax() such that any pending writes will become visible as + * expected. + */ +#define cpu_relax() smp_mb() +#else +#define cpu_relax() barrier() +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_VDSO_PROCESSOR_H */