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+0000 (GMT) Received: from epsmgms1p2new.samsung.com (unknown [182.195.42.42]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20200319150703epsmtrp2f81c05237b5626a37b2833aa1e846dc5~9vPlgaxh41476414764epsmtrp2S; Thu, 19 Mar 2020 15:07:03 +0000 (GMT) X-AuditID: b6c32a49-8b3ff700000012ae-ab-5e738a97c43a Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2new.samsung.com (Symantec Messaging Gateway) with SMTP id 74.C7.04158.79A837E5; Fri, 20 Mar 2020 00:07:03 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20200319150701epsmtip29c57472630a1383081538127fc2ee78c~9vPjyxKYS0556705567epsmtip2W; Thu, 19 Mar 2020 15:07:01 +0000 (GMT) From: Alim Akhtar To: robh+dt@kernel.org, devicetree@vger.kernel.org, linux-scsi@vger.kernel.org Subject: [PATCH v3 1/5] dt-bindings: phy: Document Samsung UFS PHY bindings Date: Thu, 19 Mar 2020 20:30:27 +0530 Message-Id: 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linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch documents Samsung UFS PHY device tree bindings Signed-off-by: Alim Akhtar --- .../bindings/phy/samsung,ufs-phy.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml base-commit: fb33c6510d5595144d585aa194d377cf74d31911 diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml new file mode 100644 index 000000000000..df54129004e9 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series UFS PHY Device Tree Bindings + +maintainers: + - Alim Akhtar + +properties: + "#phy-cells": + const: 0 + + compatible: + enum: + - samsung,exynos7-ufs-phy + + reg: + maxItems: 1 + description: PHY base register address + + reg-names: + items: + - const: phy-pma + + clocks: + items: + - description: PLL reference clock + - description: Referencec clock parrent + + clock-names: + items: + - const: ref_clk_parent + - const: ref_clk + +required: + - "#phy-cells" + - compatible + - reg + - reg-names + - clocks + - clock-names + +examples: + - | + #include + + ufs_phy: ufs-phy@0x15571800 { + compatible = "samsung,exynos7-ufs-phy"; + reg = <0x15571800 0x240>; + reg-names = "phy-pma"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + clocks = <&clock_fsys1 MOUT_FSYS1_PHYCLK_SEL1>, + <&clock_top1 CLK_SCLK_PHY_FSYS1_26M>; + clock-names = "ref_clk_parent", + "ref_clk"; + }; + +...