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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id g3sm1793431wrm.66.2020.04.01.00.37.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Apr 2020 00:37:35 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de Subject: [PATCH v1 2/2] arm64: dts: rockchip: add #phy-cells to all usb2-phy nodes Date: Wed, 1 Apr 2020 09:37:25 +0200 Message-Id: <20200401073725.6063-2-jbx6244@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20200401073725.6063-1-jbx6244@gmail.com> References: <20200401073725.6063-1-jbx6244@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200401_003737_373063_7076BB96 X-CRM114-Status: GOOD ( 15.65 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:343 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [jbx6244[at]gmail.com] 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [jbx6244[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Current dts files for Rockchip with 'usb2-phy' subnodes are manually verified. In order to automate this process phy-rockchip-inno-usb2.txt has been converted to yaml. 'usb2-phy' nodes are now checked by: 'phy-rockchip-inno-usb2.yaml' and 'phy-provider.yaml'. '#phy-cells' is now required for all usb2-phy nodes, so add them. make -k ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/ phy/phy-rockchip-inno-usb2.yaml Signed-off-by: Johan Jonker --- arch/arm64/boot/dts/rockchip/px30.dtsi | 5 +++-- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 3 ++- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++++-- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index bd5f51d23..6f7171290 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -822,10 +822,11 @@ reg = <0x100 0x20>; clocks = <&pmucru SCLK_USBPHY_REF>; clock-names = "phyclk"; - #clock-cells = <0>; + clock-output-names = "usb480m_phy"; assigned-clocks = <&cru USB480M>; assigned-clock-parents = <&u2phy>; - clock-output-names = "usb480m_phy"; + #clock-cells = <0>; + #phy-cells = <0>; status = "disabled"; u2phy_host: host-port { diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 8976c869f..470783a48 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -830,9 +830,10 @@ clocks = <&xin24m>; clock-names = "phyclk"; clock-output-names = "usb480m_phy"; - #clock-cells = <0>; assigned-clocks = <&cru USB480M>; assigned-clock-parents = <&u2phy>; + #clock-cells = <0>; + #phy-cells = <0>; status = "disabled"; u2phy_otg: otg-port { diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 3dc8fe620..a7ee5aa65 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1391,8 +1391,9 @@ reg = <0xe450 0x10>; clocks = <&cru SCLK_USB2PHY0_REF>; clock-names = "phyclk"; - #clock-cells = <0>; clock-output-names = "clk_usbphy0_480m"; + #clock-cells = <0>; + #phy-cells = <0>; status = "disabled"; u2phy0_host: host-port { @@ -1418,8 +1419,9 @@ reg = <0xe460 0x10>; clocks = <&cru SCLK_USB2PHY1_REF>; clock-names = "phyclk"; - #clock-cells = <0>; clock-output-names = "clk_usbphy1_480m"; + #clock-cells = <0>; + #phy-cells = <0>; status = "disabled"; u2phy1_host: host-port {