| Message ID | 20200417125753.13021-12-kishon@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add PCIe support to TI's J721E SoC | expand |
On Fri, Apr 17, 2020 at 06:27:50PM +0530, Kishon Vijay Abraham I wrote: > Add PCIe EP mode dt-bindings for TI's J721E SoC. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > .../bindings/pci/ti,j721e-pci-ep.yaml | 89 +++++++++++++++++++ > 1 file changed, 89 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml > > diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml > new file mode 100644 > index 000000000000..cb25c45d5a96 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml > @@ -0,0 +1,89 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: TI J721E PCI EP (PCIe Wrapper) > + > +maintainers: > + - Kishon Vijay Abraham I <kishon@ti.com> > + > +allOf: > + - $ref: "cdns-pcie-ep.yaml#" > + > +properties: > + compatible: > + enum: > + - ti,j721e-pcie-ep Wrong indentation. Otherwise, Reviewed-by: Rob Herring <robh@kernel.org> > + > + reg: > + maxItems: 4 > + > + reg-names: > + items: > + - const: intd_cfg > + - const: user_cfg > + - const: reg > + - const: mem > + > + ti,syscon-pcie-ctrl: > + description: Phandle to the SYSCON entry required for configuring PCIe mode > + and link speed. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/phandle > + > + power-domains: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + description: clock-specifier to represent input to the PCIe > + > + clock-names: > + items: > + - const: fck > + > + dma-coherent: > + description: Indicates that the PCIe IP block can ensure the coherency > + > +required: > + - compatible > + - reg > + - reg-names > + - ti,syscon-pcie-ctrl > + - max-link-speed > + - num-lanes > + - power-domains > + - clocks > + - clock-names > + - cdns,max-outbound-regions > + - dma-coherent > + - max-functions > + - phys > + - phy-names > + > +examples: > + - | > + #include <dt-bindings/soc/ti,sci_pm_domain.h> > + > + pcie0_ep: pcie-ep@d000000 { > + compatible = "ti,j721e-pcie-ep"; > + reg = <0x00 0x02900000 0x00 0x1000>, > + <0x00 0x02907000 0x00 0x400>, > + <0x00 0x0d000000 0x00 0x00800000>, > + <0x00 0x10000000 0x00 0x08000000>; > + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; > + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; > + max-link-speed = <3>; > + num-lanes = <2>; > + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 239 1>; > + clock-names = "fck"; > + cdns,max-outbound-regions = <16>; > + max-functions = /bits/ 8 <6>; > + dma-coherent; > + phys = <&serdes0_pcie_link>; > + phy-names = "pcie-phy"; > + }; > -- > 2.17.1 >
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml new file mode 100644 index 000000000000..cb25c45d5a96 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI J721E PCI EP (PCIe Wrapper) + +maintainers: + - Kishon Vijay Abraham I <kishon@ti.com> + +allOf: + - $ref: "cdns-pcie-ep.yaml#" + +properties: + compatible: + enum: + - ti,j721e-pcie-ep + + reg: + maxItems: 4 + + reg-names: + items: + - const: intd_cfg + - const: user_cfg + - const: reg + - const: mem + + ti,syscon-pcie-ctrl: + description: Phandle to the SYSCON entry required for configuring PCIe mode + and link speed. + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + description: clock-specifier to represent input to the PCIe + + clock-names: + items: + - const: fck + + dma-coherent: + description: Indicates that the PCIe IP block can ensure the coherency + +required: + - compatible + - reg + - reg-names + - ti,syscon-pcie-ctrl + - max-link-speed + - num-lanes + - power-domains + - clocks + - clock-names + - cdns,max-outbound-regions + - dma-coherent + - max-functions + - phys + - phy-names + +examples: + - | + #include <dt-bindings/soc/ti,sci_pm_domain.h> + + pcie0_ep: pcie-ep@d000000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + dma-coherent; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + };
Add PCIe EP mode dt-bindings for TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- .../bindings/pci/ti,j721e-pci-ep.yaml | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml