diff mbox series

[v4,2/2] arm64: dts: uniphier: Add support for Akebi96

Message ID 20200422115035.2f8d48843793d0d6f6724522@linaro.org (mailing list archive)
State New, archived
Headers show
Series dts: uniphier: Add Akebi96 Board support | expand

Commit Message

Masami Hiramatsu April 22, 2020, 2:50 a.m. UTC 
Add the device tree for Akebi96. Akebi96 is a 96boards certified
development board based on UniPhir LD20.
( https://www.96boards.org/product/akebi96/ )

This board has;
- MAX3421 USB-SPI chip on SPI port3 (for USB gadget port)
- Simple frame buffer with 1080p fixed resolution.
- I2S port which is connected to aout1b instead of aout1.
- 3 serial ports, only serial3 has CTS/RTS.
- No NAND, only eMMC on the board.
- OP-TEE installed firmware.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 Changes in v4:
  - Fix to remove unnecessary "aout1" from pinctrl_aout1.
---
 arch/arm64/boot/dts/socionext/Makefile             |    1 
 .../boot/dts/socionext/uniphier-ld20-akebi96.dts   |  190 ++++++++++++++++++++
 2 files changed, 191 insertions(+)
 create mode 100644 arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts

Comments

Masahiro Yamada April 22, 2020, 3:08 p.m. UTC | #1 
Hiramatsu-san

On Wed, Apr 22, 2020 at 11:50 AM Masami Hiramatsu
<masami.hiramatsu@linaro.org> wrote:

> +
> +&eth {
> +       status = "okay";
> +       phy-mode = "rgmii";
> +       pinctrl-0 = <&pinctrl_ether_rgmii>;

These two lines are actually redundant because RGMII
is the default in uniphier-ld20.dtsi
(and uniphier-ld20-ref.dts skips them.)

Did you intentionally make it verbose?




> +       phy-handle = <&ethphy>;
> +};
> +
> +&mdio {
> +       ethphy: ethphy@0 {
> +               reg = <0>;
> +       };
> +};
> +
> +&usb {
> +       status = "okay";
> +};
> +
> +&pcie {
> +       status = "okay";
> +};
> +
> +&i2c0 {
> +       /* LS connector I2C0 */
> +       status = "okay";
> +};
> +
> +&i2c1 {
> +       /* LS connector I2C1 */
> +       status = "okay";
> +};
> +
> +&spi3 {
> +       status = "okay";
> +       #address-cells = <1>;
> +       #size-cells = <0>;

Adding #address-cells and #size-sizes to a board DTS
is strange.

I will apply this:
https://lore.kernel.org/patchwork/patch/1229497/
then delete the lines above.




--
Best Regards


Masahiro Yamada
Masami Hiramatsu April 22, 2020, 3:35 p.m. UTC | #2 
Hello Yamada-san,

2020年4月23日(木) 0:10 Masahiro Yamada <masahiroy@kernel.org>:
>
> Hiramatsu-san
>
> On Wed, Apr 22, 2020 at 11:50 AM Masami Hiramatsu
> <masami.hiramatsu@linaro.org> wrote:
>
> > +
> > +&eth {
> > +       status = "okay";
> > +       phy-mode = "rgmii";
> > +       pinctrl-0 = <&pinctrl_ether_rgmii>;
>
> These two lines are actually redundant because RGMII
> is the default in uniphier-ld20.dtsi
> (and uniphier-ld20-ref.dts skips them.)
>
> Did you intentionally make it verbose?

Oops, no, we don't need it. It's a legacy code (IIRC, there's a
historical reason).


> > +&spi3 {
> > +       status = "okay";
> > +       #address-cells = <1>;
> > +       #size-cells = <0>;
>
> Adding #address-cells and #size-sizes to a board DTS
> is strange.

Indeed.

> I will apply this:
> https://lore.kernel.org/patchwork/patch/1229497/
> then delete the lines above.

OK, I'll update.

Thank you,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/socionext/Makefile b/arch/arm64/boot/dts/socionext/Makefile
index d45441249cb5..dda3da33614b 100644
--- a/arch/arm64/boot/dts/socionext/Makefile
+++ b/arch/arm64/boot/dts/socionext/Makefile
@@ -2,6 +2,7 @@ 
 dtb-$(CONFIG_ARCH_UNIPHIER) += \
 	uniphier-ld11-global.dtb \
 	uniphier-ld11-ref.dtb \
+	uniphier-ld20-akebi96.dtb \
 	uniphier-ld20-global.dtb \
 	uniphier-ld20-ref.dtb \
 	uniphier-pxs3-ref.dtb
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts
new file mode 100644
index 000000000000..c0673b2d2c89
--- /dev/null
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts
@@ -0,0 +1,190 @@ 
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for Akebi96 Development Board
+//
+// Derived from uniphier-ld20-global.dts.
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+// Copyright (C) 2019-2020 Linaro Ltd.
+
+/dts-v1/;
+#include <dt-bindings/gpio/uniphier-gpio.h>
+#include "uniphier-ld20.dtsi"
+
+/ {
+	model = "Akebi96";
+	compatible = "socionext,uniphier-ld20-akebi96",
+		     "socionext,uniphier-ld20";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		spi2 = &spi2;
+		spi3 = &spi3;
+		ethernet0 = &eth;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0xc0000000>;
+	};
+
+	framebuffer {
+		compatible = "simple-framebuffer";
+		reg = <0 0xc0000000 0 0x02000000>;
+		width = <1920>;
+		height = <1080>;
+		stride = <7680>;
+		format = "a8r8g8b8";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		memory@c0000000 {
+			reg = <0 0xc0000000 0 0x02000000>;
+			no-map;
+		};
+	};
+
+	sound {
+		compatible = "audio-graph-card";
+		label = "UniPhier LD20";
+		dais = <&spdif_port0
+			&comp_spdif_port0>;
+	};
+
+	spdif-out {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+
+		port@0 {
+			spdif_tx: endpoint {
+				remote-endpoint = <&spdif_hiecout1>;
+			};
+		};
+	};
+
+	comp-spdif-out {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+
+		port@0 {
+			comp_spdif_tx: endpoint {
+				remote-endpoint = <&comp_spdif_hiecout1>;
+			};
+		};
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+
+&serial0 {
+	/* Onboard USB-UART */
+	status = "okay";
+};
+
+&serial2 {
+	/* LS connector UART1 */
+	status = "okay";
+};
+
+&serial3 {
+	/* LS connector UART0 */
+	status = "okay";
+};
+
+&spdif_hiecout1 {
+	remote-endpoint = <&spdif_tx>;
+};
+
+&comp_spdif_hiecout1 {
+	remote-endpoint = <&comp_spdif_tx>;
+};
+
+&eth {
+	status = "okay";
+	phy-mode = "rgmii";
+	pinctrl-0 = <&pinctrl_ether_rgmii>;
+	phy-handle = <&ethphy>;
+};
+
+&mdio {
+	ethphy: ethphy@0 {
+		reg = <0>;
+	};
+};
+
+&usb {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&i2c0 {
+	/* LS connector I2C0 */
+	status = "okay";
+};
+
+&i2c1 {
+	/* LS connector I2C1 */
+	status = "okay";
+};
+
+&spi3 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	usb-over-spi@0 {
+		compatible = "maxim,max3421-udc";
+		reg = <0>;
+		spi-max-frequency = <12500000>;
+		interrupt-parent = <&gpio>;
+		interrupts = <0 2>, <10 3>;
+	};
+};
+
+&gpio {
+	/* IRQs for Max3421 */
+	xirq0 {
+		gpio-hog;
+		gpios = <UNIPHIER_GPIO_IRQ(0) 1>;
+		input;
+	};
+	xirq10 {
+		gpio-hog;
+		gpios = <UNIPHIER_GPIO_IRQ(10) 1>;
+		input;
+	};
+};
+
+&pinctrl_aout1 {
+	groups = "aout1b";
+};
+
+&pinctrl_uart3 {
+	groups = "uart3", "uart3_ctsrts";
+};