@@ -228,36 +228,6 @@ osc32k: clk-32k {
clock-output-names = "ext_osc32k";
};
- /*
- * The following two are dummy clocks, placeholders
- * used in the gmac_tx clock. The gmac driver will
- * choose one parent depending on the PHY interface
- * mode, using clk_set_rate auto-reparenting.
- *
- * The actual TX clock rate is not controlled by the
- * gmac_tx clock.
- */
- mii_phy_tx_clk: clk-mii-phy-tx {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <25000000>;
- clock-output-names = "mii_phy_tx";
- };
-
- gmac_int_tx_clk: clk-gmac-int-tx {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "gmac_int_tx";
- };
-
- gmac_tx_clk: clk@1c200d0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun7i-a20-gmac-clk";
- reg = <0x01c200d0 0x4>;
- clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
- clock-output-names = "gmac_tx";
- };
};
de: display-engine {
@@ -943,11 +913,12 @@ i2c3: i2c@1c2b800 {
gmac: ethernet@1c30000 {
compatible = "allwinner,sun7i-a20-gmac";
+ syscon = <&ccu>;
reg = <0x01c30000 0x1054>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
- clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
- clock-names = "stmmaceth", "allwinner_gmac_tx";
+ clocks = <&ccu CLK_AHB1_EMAC>;
+ clock-names = "stmmaceth";
resets = <&ccu RST_AHB1_EMAC>;
reset-names = "stmmaceth";
snps,pbl = <2>;
Use syscon-based approach to access gmac clock configuration register instead of relying on a custom clock driver. As a bonus, we can now drop the custom clock implementation and the dummy clocks. Signed-off-by: Priit Laes <plaes@plaes.org> --- arch/arm/boot/dts/sun6i-a31.dtsi | 35 +++----------------------------- 1 file changed, 3 insertions(+), 32 deletions(-)