| Message ID | 20200525091544.17270-14-p.yadav@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mtd: spi-nor: add xSPI Octal DTR support | expand |
On Monday, May 25, 2020 12:15:38 PM EEST Pratyush Yadav wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > The Micron MT35XU512ABA flash does not support the quad enable bit. But > instead of programming the Quad Enable Require field to 000b ("Device > does not have a QE bit"), it is programmed to 111b ("Reserved"). > > While this is technically incorrect, it is not reason enough to abort > BFPT parsing. Instead, continue BFPT parsing assuming there is no quad > enable bit present. > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > --- > drivers/mtd/spi-nor/sfdp.c | 8 +++----- > 1 file changed, 3 insertions(+), 5 deletions(-) > > diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c > index 052cabb52df9..9fd3d8d9a127 100644 > --- a/drivers/mtd/spi-nor/sfdp.c > +++ b/drivers/mtd/spi-nor/sfdp.c > @@ -576,10 +576,6 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, > > /* Quad Enable Requirements. */ > switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) { > - case BFPT_DWORD15_QER_NONE: > - params->quad_enable = NULL; > - break; > - > case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: > /* > * Writing only one byte to the Status Register has the > @@ -616,8 +612,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, > params->quad_enable = spi_nor_sr2_bit1_quad_enable; > break; > > + case BFPT_DWORD15_QER_NONE: > default: > - return -EINVAL; > + params->quad_enable = NULL; > + break; I would just add a dev_dbg message and break the switch. dev_dbg(nor->dev, "BFPT QER reserved value used.\n"); break; You will then have to set params->quad_enable = NULL; in a post_bfpt hook. Cheers, ta
Hi Tudor, On 30/05/20 06:42PM, Tudor.Ambarus@microchip.com wrote: > On Monday, May 25, 2020 12:15:38 PM EEST Pratyush Yadav wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > > content is safe > > > > The Micron MT35XU512ABA flash does not support the quad enable bit. But > > instead of programming the Quad Enable Require field to 000b ("Device > > does not have a QE bit"), it is programmed to 111b ("Reserved"). > > > > While this is technically incorrect, it is not reason enough to abort > > BFPT parsing. Instead, continue BFPT parsing assuming there is no quad > > enable bit present. > > > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > > --- > > drivers/mtd/spi-nor/sfdp.c | 8 +++----- > > 1 file changed, 3 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c > > index 052cabb52df9..9fd3d8d9a127 100644 > > --- a/drivers/mtd/spi-nor/sfdp.c > > +++ b/drivers/mtd/spi-nor/sfdp.c > > @@ -576,10 +576,6 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, > > > > /* Quad Enable Requirements. */ > > switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) { > > - case BFPT_DWORD15_QER_NONE: > > - params->quad_enable = NULL; > > - break; > > - > > case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: > > /* > > * Writing only one byte to the Status Register has the > > @@ -616,8 +612,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, > > params->quad_enable = spi_nor_sr2_bit1_quad_enable; > > break; > > > > + case BFPT_DWORD15_QER_NONE: > > default: > > - return -EINVAL; > > + params->quad_enable = NULL; > > + break; > > I would just add a dev_dbg message and break the switch. > dev_dbg(nor->dev, "BFPT QER reserved value used.\n"); > break; > > You will then have to set params->quad_enable = NULL; in a post_bfpt hook. Ok. Will re-roll. BTW, are you planning to pick up the xSPI/8D support for 5.8? It has been outstanding for quite some time now and it would be great if it can make it through this merge window.
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 052cabb52df9..9fd3d8d9a127 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -576,10 +576,6 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, /* Quad Enable Requirements. */ switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) { - case BFPT_DWORD15_QER_NONE: - params->quad_enable = NULL; - break; - case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: /* * Writing only one byte to the Status Register has the @@ -616,8 +612,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, params->quad_enable = spi_nor_sr2_bit1_quad_enable; break; + case BFPT_DWORD15_QER_NONE: default: - return -EINVAL; + params->quad_enable = NULL; + break; } /* Stop here if JESD216 rev B. */
The Micron MT35XU512ABA flash does not support the quad enable bit. But instead of programming the Quad Enable Require field to 000b ("Device does not have a QE bit"), it is programmed to 111b ("Reserved"). While this is technically incorrect, it is not reason enough to abort BFPT parsing. Instead, continue BFPT parsing assuming there is no quad enable bit present. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> --- drivers/mtd/spi-nor/sfdp.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-)