@@ -67,13 +67,13 @@
* until either the TLB entry is evicted under pressure, or a context
* switch which changes the user space mapping occurs.
*/
-#define PTRS_PER_PTE 512
+#define PTRS_PER_PTE (512 >> (PAGE_SHIFT-12))
#define PTRS_PER_PMD 1
#define PTRS_PER_PGD 2048
-#define PTE_HWTABLE_PTRS (PTRS_PER_PTE)
+#define PTE_HWTABLE_PTRS (512)
#define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t))
-#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32))
+#define PTE_HWTABLE_SIZE (PTE_HWTABLE_PTRS * sizeof(u32))
/*
* PMD_SHIFT determines the size of the area a second-level page table can map
With 4 KB pages, each page table contained 512 entries in the hardware page tables, and 512 entries in the Linux page tables, each of those entries pointing to 4 KB page. With larger page sizes being emulated, the hardware page tables will continue to contain 512 entries, as we keep using 4 KB pages at the MMU level. Hence PTE_HWTABLE_PTRS is changed to 512. However, the number of Linux page tables entries will vary depending on the page size: 512 entries with 4 KB pages, 256 entries with 8 KB pages, 128 entries with 16 KB pages, etc. In the case of 4K pages, this patch doesn't modify the values being used. This is inspired from fa0ca2726ea9 ("DSMP 64K support") and 4ef803e12baf ("mmu: large-page: Added support for multiple kernel page sizes") from https://github.com/MarvellEmbeddedProcessors/linux-marvell.git Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> --- arch/arm/include/asm/pgtable-2level.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)