Message ID | 20200616135238.3001888-44-thierry.reding@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Tue, 16 Jun 2020 06:54:31 -0700 (PDT) From: Thierry Reding <thierry.reding@gmail.com> To: Thierry Reding <thierry.reding@gmail.com> Subject: [PATCH 43/73] arm64: tegra: Add interrupt for Tegra194 memory controller Date: Tue, 16 Jun 2020 15:52:08 +0200 Message-Id: <20200616135238.3001888-44-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200616_065436_217934_E5543161 X-CRM114-Status: UNSURE ( 9.57 ) X-CRM114-Notice: Please train this message. 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Series |
ARM: tegra: Various fixes for DT schema validation
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diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index a50504a317d7..73aba724bf67 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -179,6 +179,7 @@ mc: memory-controller@2c00000 { reg = <0x02c00000 0x100000>, <0x02b80000 0x040000>, <0x01700000 0x100000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; #interconnect-cells = <1>; status = "disabled";