Message ID | 20200616135238.3001888-74-thierry.reding@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Tue, 16 Jun 2020 06:55:37 -0700 (PDT) From: Thierry Reding <thierry.reding@gmail.com> To: Thierry Reding <thierry.reding@gmail.com> Subject: [PATCH 73/73] arm64: tegra: Fix order of XUSB controller clocks Date: Tue, 16 Jun 2020 15:52:38 +0200 Message-Id: <20200616135238.3001888-74-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200616_065539_543726_E02A43A3 X-CRM114-Status: UNSURE ( 9.41 ) X-CRM114-Notice: Please train this message. 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Series |
ARM: tegra: Various fixes for DT schema validation
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diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index c265211f8a84..b9c6ba707ef9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -997,8 +997,8 @@ usb@70090000 { <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA210_CLK_XUSB_SS>, - <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA210_CLK_PLL_U_480M>, @@ -1006,7 +1006,7 @@ usb@70090000 { <&tegra_car TEGRA210_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_div2", "xusb_ss_src", + "xusb_ss_src", "xusb_ss_div2", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>,