From patchwork Thu Jul 2 10:13:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11638425 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8C0F96C1 for ; Thu, 2 Jul 2020 10:15:41 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A7093207E8 for ; Thu, 2 Jul 2020 10:15:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="2rPoG43d"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Rv9S5jNJ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A7093207E8 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=pT5maK3nwe0uPv/sooTrh8SWsTJzsELn73gEneQytQI=; b=2rPoG43dOmRb8p1vQG5WMucNF +FF37UKEY+n11qrfKhfOxgzsuhjQYyXJQroCJuNihlsrhrBb6zpFd8zUAhHmhGZtBF+FzGwajZe1P MTQ6F6sdhkUwpdSgLHhbH9ZNhbec2CLXsXM1iSnXhS5TxnVV2J45WHOG3IXJuEsmQgouH0OnPI+rG zpvUaNhnyEJ1ZYGVM1DaQ+oJIptsdn2ZcKaDXF66RVKlUmvqzNwqzHvMmD16vQbIt74YmwcR7q/2w lJUpl85sP+zfXNHjGBvnYw41o13EDB6WF4DW2Pm5+/4a9KEiYOoSCnB34AEuY1Wio004q96FClDhi m5DpOmihQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqwEU-0007ZE-Nq; Thu, 02 Jul 2020 10:14:18 +0000 Received: from esa4.microchip.iphmx.com ([68.232.154.123]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqwER-0007Wu-DH for linux-arm-kernel@lists.infradead.org; Thu, 02 Jul 2020 10:14:16 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1593684855; x=1625220855; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b2ugvk1PicikjR6ydZwpp/7jv6no2O2VLW8Gbo1OcRQ=; b=Rv9S5jNJpZvAjpGNtF6rsKVQrk0ZTPDGKmMecKzRAHoDABpDwlIyVw/0 NdiVf2LIOEmII26dFHvSoVsRZjG6M569B3Hf1TP2a9mjZiMbSpJPcOe1T 8Q1WlbsDz8KcDmk9q9YvW2Vkc+LhIfuKDyHjhk7CDnGA6IL4fKE8s1uY2 EvxcO08U7zUQ9UCg6ZWfbDR8DHyDUOgO7czykUAMrTR0kDmfeSD4z2V8n ywC79SjyjggSxq5WspfGrEoerebIK5cQhl0ZVqk8WhNc2SpF6mYQWaqU7 BJwSzuinjRPLLOIKd48lJus/fRL3Po1E2HBJoWiqJqDP/KwFiN8VdBWQ8 Q==; IronPort-SDR: d2V5dIa7z2Erui3Yniq+zNX2vG7Ee3Arao2iGg1o7kqaXM7+Rhqa5rg72q8msIOcNC+DwFx8Nr d46HN7alaVlUnIesuS5kVPYK1ddn2qHu7IA1curO4QyuENWhcDUJRfYgOOunHAgjL3x5SPpVr/ 0kzsIWQS8Bvh59gv+NFbNCBWS7BAkhykB9PWJi9wiOa08ykG0g13F2l3GM+uKQsbxCOzlo+Hoq ccuv9EI5GkLERvzKvYIfchT564MGV/Xj9y4uG2Dohisy/vGOKpksAkFqLfW+rMpyzA+P7GZ0sA axg= X-IronPort-AV: E=Sophos;i="5.75,304,1589266800"; d="scan'208";a="78545355" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 02 Jul 2020 03:14:14 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 2 Jul 2020 03:14:13 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 2 Jul 2020 03:13:51 -0700 From: Lars Povlsen To: Mark Brown , Peter Rosin Subject: [PATCH v3 2/8] arm64: dts: sparx5: Add SPI controller and SPI mux Date: Thu, 2 Jul 2020 12:13:25 +0200 Message-ID: <20200702101331.26375-3-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200702101331.26375-1-lars.povlsen@microchip.com> References: <20200702101331.26375-1-lars.povlsen@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200702_061415_672632_AC40B468 X-CRM114-Status: UNSURE ( 7.05 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.154.123 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [68.232.154.123 listed in wl.mailspike.net] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Serge Semin , linux-spi@vger.kernel.org, Serge Semin , Lars Povlsen , Microchip Linux Driver Support , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This adds a SPI controller to the Microchip Sparx5 SoC, as well as the SPI bus interface mux, which may optionally be needed for selecting between alternate SPI bus segments (SPI/SPI2). Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 7e811e24f0e99..2831935a489e1 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -14,6 +14,8 @@ / { #size-cells = <1>; aliases { + mux = &mux; + spi0 = &spi0; serial0 = &uart0; serial1 = &uart1; }; @@ -155,6 +157,27 @@ uart1: serial@600102000 { status = "disabled"; }; + mux: mux-controller { + compatible = "microchip,sparx5-spi-mux"; + #address-cells = <1>; + #size-cells = <0>; + #mux-control-cells = <0>; + }; + + spi0: spi@600104000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-spi"; + reg = <0x6 0x00104000 0x40>; + num-cs = <16>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ahb_clk>; + interrupts = ; + mux-controls = <&mux>; + status = "disabled"; + }; + timer1: timer@600105000 { compatible = "snps,dw-apb-timer"; reg = <0x6 0x00105000 0x1000>;