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Mon, 20 Jul 2020 21:40:36 -0800 Received: from mtkmbs08n2.mediatek.inc (172.21.101.56) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 20 Jul 2020 22:40:37 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 21 Jul 2020 13:40:35 +0800 Received: from mtkslt209.mediatek.inc (10.21.15.96) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 21 Jul 2020 13:40:35 +0800 From: Hanks Chen To: Michael Turquette , Stephen Boyd , Matthias Brugger , Rob Herring Subject: [PATCH 2/2] clk: mediatek: remove UART3 clock support Date: Tue, 21 Jul 2020 13:40:33 +0800 Message-ID: <20200721054033.18520-3-hanks.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200721054033.18520-1-hanks.chen@mediatek.com> References: <20200721054033.18520-1-hanks.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 260778E1BAA8E2DC087EAC720C4C06B45F5F973202C578C7CC33AA0E0F17F9CE2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200721_014057_823126_4D9F5862 X-CRM114-Status: GOOD ( 10.09 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: CC Hwang , wsd_upstream@mediatek.com, Hanks Chen , YueHaibing , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mediatek@lists.infradead.org, mtk01761 , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org CLK_INFRA_UART3 is a dummy clk interface, it has no effect on the operation of the read/write instruction. Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") Signed-off-by: Hanks Chen --- drivers/clk/mediatek/clk-mt6779.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 9766cccf5844..75f2235486be 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -923,8 +923,6 @@ static const struct mtk_gate infra_clks[] = { "uart_sel", 23), GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), - GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", - "uart_sel", 25), GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27), GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",