| Message ID | 20200722203341.578651-1-cphealy@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] ARM: dts: ZII: Disable HW Ethernet switch reset GPIOs | expand |
Hi Chris, On Wed, Jul 22, 2020 at 5:33 PM Chris Healy <cphealy@gmail.com> wrote: > > From: Chris Healy <cphealy@gmail.com> > > Disable Ethernet switch reset GPIO with ZII platforms that have it > enabled. HW switch reset results in a reset of the copper PHYs > inside of the switch. We want to avoid this reset of the copper PHYs > in the switch as this results in unnecessary broader network disruption on > a soft reboot of the application processor. > > With the HW GPIO removed, the switch driver still performs a soft reset of > the switch core which has been shown to sufficiently meet our needs with > other ZII platforms that do not have the HW switch reset GPIO defined. > > Signed-off-by: Chris Healy <cphealy@gmail.com> > --- > v2: > - Update the description to more accurately reflect why we are making the change Updated description is clear now: Reviewed-by: Fabio Estevam <festevam@gmail.com>
On Wed, Jul 22, 2020 at 01:33:41PM -0700, Chris Healy wrote: > From: Chris Healy <cphealy@gmail.com> > > Disable Ethernet switch reset GPIO with ZII platforms that have it > enabled. HW switch reset results in a reset of the copper PHYs > inside of the switch. We want to avoid this reset of the copper PHYs > in the switch as this results in unnecessary broader network disruption on > a soft reboot of the application processor. > > With the HW GPIO removed, the switch driver still performs a soft reset of > the switch core which has been shown to sufficiently meet our needs with > other ZII platforms that do not have the HW switch reset GPIO defined. > > Signed-off-by: Chris Healy <cphealy@gmail.com> Applied, thanks.
diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 64e0e9509226..50da0c94e1b7 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -172,7 +172,6 @@ switch0: switch0@0 { interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <2>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; ports { #address-cells = <1>; @@ -356,7 +355,6 @@ VF610_PAD_PTE13__GPIO_118 0x3043 pinctrl_switch: switch-grp { fsl,pins = < VF610_PAD_PTB28__GPIO_98 0x3061 - VF610_PAD_PTE2__GPIO_107 0x1042 >; }; diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts index 9e5187ba3fa6..6c6ec46fd015 100644 --- a/arch/arm/boot/dts/vf610-zii-spb4.dts +++ b/arch/arm/boot/dts/vf610-zii-spb4.dts @@ -129,7 +129,6 @@ switch0: switch0@0 { pinctrl-names = "default"; reg = <0>; eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -326,7 +325,6 @@ VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 pinctrl_gpio_switch0: pinctrl-gpio-switch0 { fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 VF610_PAD_PTB28__GPIO_98 0x219d >; }; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts index 569614b08f04..73fdace4cb42 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts @@ -118,7 +118,6 @@ switch0: switch0@0 { pinctrl-names = "default"; reg = <0>; eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -293,7 +292,6 @@ VF610_PAD_PTB24__GPIO_94 0x219d pinctrl_gpio_switch0: pinctrl-gpio-switch0 { fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 VF610_PAD_PTB28__GPIO_98 0x219d >; }; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index b6b0f302b7b4..fe600ab2e4bd 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -143,7 +143,6 @@ switch0: switch0@0 { pinctrl-names = "default"; reg = <0>; eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -333,7 +332,6 @@ VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 pinctrl_gpio_switch0: pinctrl-gpio-switch0 { fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 VF610_PAD_PTB28__GPIO_98 0x219d >; };