From patchwork Fri Jul 31 09:44:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Elisei X-Patchwork-Id: 11694583 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E3DBD1392 for ; Fri, 31 Jul 2020 09:45:30 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B8A1A20663 for ; Fri, 31 Jul 2020 09:45:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="HYYg6u3y" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B8A1A20663 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=wt1b/ZYAV2AKDeKQj4IN30bW+3Wu22jX6LTxVdqGk84=; b=HYYg6u3yrmVx2GcDAbRaN3ugEW 3tNCurT+5sDzk/RNeGE/9pa12PrJMIUn4vrxjTuXhYl8J5ArC6ySyAiZOLhNocxV3nqTWO4yMJCCD KkCYh6YZOleAWrQ1s2mKAgDo/VC+xEoToKucpPupPkdE4Cc9hq1YN5gTlXuJ94T0Y4sXel6eeHOKp TgEjE/zxDINZ1l2aEmNSSubYRMjCujfMAdz2amp2GeLviir1/ffYbCvqof7cmClzWwPn8b/8rkVix ipbN6yIVCL5YdzmYhxu4FSlSYHB1fFIPW2HfM+JHt5fXVZkcivTrc2urVOB06YATl2+u75yfe4pr6 SzL3I11g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k1Ra8-0003Py-22; Fri, 31 Jul 2020 09:44:04 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k1Ra4-0003OR-Rf for linux-arm-kernel@lists.infradead.org; Fri, 31 Jul 2020 09:44:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4BCEA31B; Fri, 31 Jul 2020 02:43:58 -0700 (PDT) Received: from monolith.localdoman (unknown [10.37.12.100]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A60303F66E; Fri, 31 Jul 2020 02:43:57 -0700 (PDT) From: Alexandru Elisei To: linux-arm-kernel@lists.infradead.org Subject: [boot-wrapper][PATCH] aarch64: Enable SPE for the non-secure world Date: Fri, 31 Jul 2020 10:44:43 +0100 Message-Id: <20200731094443.11564-1-alexandru.elisei@arm.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200731_054400_989772_0C448D1A X-CRM114-Status: GOOD ( 11.98 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org MDCR_EL3.NSPB resets to an UNKNOWN value. Configure it to allow the profiling buffer to use non-secure memory and to permit direct register accesses from the non-secure world. So far, we haven't programmed MDCR_EL3 explicitly even though there are other fields which reset to an UNKNOWN value. The majority of those, when cleared, allow lower exception levels to use the features they control; for the other fields we don't have support yet. Reset the register to zero with the exception of MDCR_EL3.NSPB. Signed-off-by: Alexandru Elisei Reviewed-by: Andre Przywara --- Tested on the model, with ARMv8.2 enabled and disabled (no SPE present). arch/aarch64/boot.S | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 74705cded338..f821b0175d4b 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -55,6 +55,17 @@ _start: msr cptr_el3, xzr // Disable copro. traps to EL3 + mov x0, xzr + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #32, #4 + cbz x1, 1f + + // Enable SPE for the non-secure world. + ldr x1, =(0x3 << 12) + orr x0, x0, x1 + +1: msr mdcr_el3, x0 // Disable traps to EL3 + mrs x0, id_aa64pfr0_el1 ubfx x0, x0, #32, #4 // SVE present? cbz x0, 1f // Skip SVE init if not