| Message ID | 20200814024114.1177553-11-robdclark@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | iommu/arm-smmu: Add Adreno SMMU specific implementation | expand |
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Jordan Crouse <jcrouse@codeaurora.org> > > Every Qcom Adreno GPU has an embedded SMMU for its own use. These > devices depend on unique features such as split pagetables, > different stall/halt requirements and other settings. Identify them > with a compatible string so that they can be identified in the > arm-smmu implementation specific code. > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index 503160a7b9a0..5ec5d0d691f6 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -40,6 +40,10 @@ properties: > - qcom,sm8150-smmu-500 > - qcom,sm8250-smmu-500 > - const: arm,mmu-500 > + - description: Qcom Adreno GPUs implementing "arm,smmu-v2" > + items: > + - const: qcom,adreno-smmu > + - const: qcom,smmu-v2 > - description: Marvell SoCs implementing "arm,mmu-500" > items: > - const: marvell,ap806-smmu-500 > -- > 2.26.2 >
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 503160a7b9a0..5ec5d0d691f6 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -40,6 +40,10 @@ properties: - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - const: arm,mmu-500 + - description: Qcom Adreno GPUs implementing "arm,smmu-v2" + items: + - const: qcom,adreno-smmu + - const: qcom,smmu-v2 - description: Marvell SoCs implementing "arm,mmu-500" items: - const: marvell,ap806-smmu-500