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Wed, 26 Aug 2020 17:15:51 +0000 (GMT) From: Sylwester Nawrocki To: linux-clk@vger.kernel.org Subject: [PATCH 2/3] clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions Date: Wed, 26 Aug 2020 19:15:28 +0200 Message-Id: <20200826171529.23618-2-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200826171529.23618-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOKsWRmVeSWpSXmKPExsWy7djPc7onZrjFG1z7rWOxccZ6VovrX56z Wsw/co7Vov/xa2aL8+c3sFtsenyN1eJjzz1Wi8u75rBZzDi/j8li7ZG77BYXT7latO49wm5x +E07q8W/axtZLFbt+sPowO/x/kYru8fOWXfZPTat6mTz2Lyk3qNvyypGj8+b5ALYorhsUlJz MstSi/TtErgy9i+5wF7wTajiXOMltgbGr/xdjJwcEgImErf33WXqYuTiEBJYwShx98lbKOcL o8SKl/uZIZzPjBJzL78BynCAtcz+xg4RX84o8evID0aQUWAdU7b6gdhsAoYSvUf7wOIiArIS t479ZANpYBb4yizRteUTE0hCWCBeYvXj1awgNouAqkTHwidgcV4Ba4krD2YwQdwnL7F6wwFm EJtTwEbi19KzYBdJCGxilzjxaQUzRJGLxK1F89ggbGGJV8e3sEPYMhKnJ/ewQDQ0M0r07L7N DuFMYJS4f3wBI0SVtcSdc7/YQH5jFtCUWL9LHyLsKPGs7R4LxMt8EjfeCoKEmYHMSdumM0OE eSU62oQgqlUkfq+aDnWzlET3k/8sELaHRMOk09DQ6meUuP3lMNsERvlZCMsWMDKuYhRPLS3O TU8tNsxLLdcrTswtLs1L10vOz93ECEw+p/8d/7SD8eulpEOMAhyMSjy8GvFu8UKsiWXFlbmH GCU4mJVEeJ3Ono4T4k1JrKxKLcqPLyrNSS0+xCjNwaIkzmu86GWskEB6YklqdmpqQWoRTJaJ g1OqgVFRWa9gzrOeyKzCNben1F7cmaCy7Mpy2RiWtZNXd+WFz9v6RGbz6bKan1mz7sRO3H5Y gz1NL+D7id3pWlun2xesL9OebfzYd/vSuwpbOK9YBy5K1f1x/bX04iAFL6snV+4w/iyqDql+ +Ey/Mu5q8fnMJ9eVTu056+iQwti6u9+idk5Cj8r+/feUWIozEg21mIuKEwGCo4W8OgMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpjkeLIzCtJLcpLzFFi42I5/e/4Xd0TM9ziDS6s47XYOGM9q8X1L89Z LeYfOcdq0f/4NbPF+fMb2C02Pb7GavGx5x6rxeVdc9gsZpzfx2Sx9shddouLp1wtWvceYbc4 /Kad1eLftY0sFqt2/WF04Pd4f6OV3WPnrLvsHptWdbJ5bF5S79G3ZRWjx+dNcgFsUXo2Rfml JakKGfnFJbZK0YYWRnqGlhZ6RiaWeobG5rFWRqZK+nY2Kak5mWWpRfp2CXoZ+5dcYC/4JlRx rvESWwPjV/4uRg4OCQETidnf2LsYuTiEBJYySjz/9YwRIi4lMb9FqYuRE8gUlvhzrYsNouYT o8SqS5uZQRJsAoYSvUf7GEFsEQFZiVvHfoIVMQs0skicnbiGFWSQsECsRM/LBJAaFgFViY6F T5hAbF4Ba4krD2YwQSyQl1i94QDYTE4BG4lfS8+C2UJANXc232KdwMi3gJFhFaNIamlxbnpu sZFecWJucWleul5yfu4mRmAcbDv2c8sOxq53wYcYBTgYlXh4NeLd4oVYE8uKK3MPMUpwMCuJ 8DqdPR0nxJuSWFmVWpQfX1Sak1p8iNEU6KiJzFKiyfnAGM0riTc0NTS3sDQ0NzY3NrNQEuft EDgYIySQnliSmp2aWpBaBNPHxMEp1cDoZsnO+v+3ymnZD0phZSvyBdmMUrYob5c4u5XHq/O3 TqRSf0XviwK+1DdiW3KWJLybLfyr99m/dW92N01Oj+D6tiZ4yzPb4rtWTH0PTy3ZnBPHuHoJ d27NwtdhzC8mv7ux5emFvtlllyY18U/xv/cvqzvrkm26wYrKCyE1b2auqOO3qircLZOuxFKc kWioxVxUnAgAjRux0JkCAAA= X-CMS-MailID: 20200826171552eucas1p28ace6b1efbcdab420aaa4458ac8bad08 X-Msg-Generator: CA X-RootMTR: 20200826171552eucas1p28ace6b1efbcdab420aaa4458ac8bad08 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200826171552eucas1p28ace6b1efbcdab420aaa4458ac8bad08 References: <20200826171529.23618-1-s.nawrocki@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200826_131555_337395_996D697E X-CRM114-Status: GOOD ( 16.40 ) X-Spam-Score: -6.2 (------) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-6.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [210.118.77.11 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [210.118.77.11 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders -1.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, Rob Herring , b.zolnierkie@samsung.com, Stephen Boyd , Michael Turquette , Tomasz Figa , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Chanwoo Choi , Kukjin Kim , Sylwester Nawrocki , linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Use non-zero clock IDs in definitions of the CPU parent clocks for exynos5420, exynos5250 SoCs. This will allow us to reference the parent clocks directly in the driver by cached struct clk_hw pointers, rather than doing clk lookup by name. Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski Acked-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos5250.c | 4 ++-- drivers/clk/samsung/clk-exynos5420.c | 11 ++++++----- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 931c70a..7bcff76 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -253,14 +253,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = { /* * CMU_CPU */ - MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, CLK_SET_RATE_PARENT, 0), MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), /* * CMU_CORE */ - MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1), + MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1), /* * CMU_TOP diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index f76ebd6..d07cee2 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -596,13 +596,14 @@ static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, SRC_TOP7, 4, 1), - MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), - MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), - - MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + MUX(CLK_MOUT_MSPLL_KFC, "mout_mspll_kfc", mout_mspll_cpu_p, + SRC_TOP7, 8, 2), + MUX(CLK_MOUT_MSPLL_CPU, "mout_mspll_cpu", mout_mspll_cpu_p, + SRC_TOP7, 12, 2), + MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), - MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, + MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),