| Message ID | 20200901140628.8800-2-kishon@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add DT to get PCIe working in J721E SoC | expand |
On 19:36-20200901, Kishon Vijay Abraham I wrote: > Add PCIe device tree node (both RC and EP) for the four > PCIe instances here. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 ++++++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- > 2 files changed, 222 insertions(+), 1 deletion(-) Did you look at the diff of the dtbs_check before and after this series? I see: https://pastebin.ubuntu.com/p/9fyfrTjx9M/ > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > index 00a36a14efe7..a36909d8b8c3 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > @@ -28,6 +28,26 @@ > #size-cells = <1>; > ranges = <0x0 0x0 0x00100000 0x1c000>; > > + pcie0_ctrl: pcie-ctrl@4070 { https://github.com/devicetree-org/devicetree-specification/releases/download/v0.3/devicetree-specification-v0.3.pdf Section 2.2.2: why not use syscon@4070 and so on? > + compatible = "syscon"; > + reg = <0x00004070 0x4>; > + }; > + > + pcie1_ctrl: pcie-ctrl@4074 { > + compatible = "syscon"; > + reg = <0x00004074 0x4>; > + }; > + > + pcie2_ctrl: pcie-ctrl@4078 { > + compatible = "syscon"; > + reg = <0x00004078 0x4>; > + }; > + > + pcie3_ctrl: pcie-ctrl@407c { > + compatible = "syscon"; > + reg = <0x0000407c 0x4>; > + }; > + > serdes_ln_ctrl: serdes-ln-ctrl@4080 { > compatible = "mmio-mux"; > reg = <0x00004080 0x50>; > @@ -576,6 +596,204 @@ > }; > }; > > + pcie0_rc: pcie@2900000 { > + compatible = "ti,j721e-pcie-host"; > + reg = <0x00 0x02900000 0x00 0x1000>, > + <0x00 0x02907000 0x00 0x400>, > + <0x00 0x0d000000 0x00 0x00800000>, > + <0x00 0x10000000 0x00 0x00001000>; > + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; > + interrupt-names = "link_state"; > + interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; > + device_type = "pci"; > + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; > + max-link-speed = <3>; > + num-lanes = <2>; > + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 239 1>; > + clock-names = "fck"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x0 0xf>; > + vendor-id = <0x104c>; > + device-id = <0xb00d>; > + msi-map = <0x0 &gic_its 0x0 0x10000>; > + dma-coherent; > + ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, > + <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; > + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; > + }; > + > + pcie0_ep: pcie-ep@2900000 { Not related to this patch, but just a suggestion: pcie-ep -> do we need to add that to the Generic names in DT spec? [...] > diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi > index f787aa73aaae..eeb02115b966 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi > @@ -132,9 +132,12 @@ > <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ > <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ > <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ > - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ > + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ > + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ > <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ ^^ should be PCIe1? Just because you are introducing PCIe2,3 in this patch, the net result does'nt look consistent? Also might want to cover this change in the $commit_message. [...] > <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ > + <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ > + <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ > <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ > <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ > <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ > -- > 2.17.1 >
Hi Nishanth, On 01/09/20 8:22 pm, Nishanth Menon wrote: > On 19:36-20200901, Kishon Vijay Abraham I wrote: >> Add PCIe device tree node (both RC and EP) for the four >> PCIe instances here. >> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >> --- >> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 ++++++++++++++++++++++ >> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- >> 2 files changed, 222 insertions(+), 1 deletion(-) > > > Did you look at the diff of the dtbs_check before and after this > series? I see: https://pastebin.ubuntu.com/p/9fyfrTjx9M/ I didn't see any errors when I checked for individual bindings a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml" SCHEMA Documentation/devicetree/bindings/processed-schema.yaml DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml" SCHEMA Documentation/devicetree/bindings/processed-schema.yaml DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml > >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >> index 00a36a14efe7..a36909d8b8c3 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >> @@ -28,6 +28,26 @@ >> #size-cells = <1>; >> ranges = <0x0 0x0 0x00100000 0x1c000>; >> >> + pcie0_ctrl: pcie-ctrl@4070 { > https://github.com/devicetree-org/devicetree-specification/releases/download/v0.3/devicetree-specification-v0.3.pdf > Section 2.2.2: why not use syscon@4070 and so on? okay, will change to generic name. > >> + compatible = "syscon"; >> + reg = <0x00004070 0x4>; >> + }; >> + >> + pcie1_ctrl: pcie-ctrl@4074 { >> + compatible = "syscon"; >> + reg = <0x00004074 0x4>; >> + }; >> + >> + pcie2_ctrl: pcie-ctrl@4078 { >> + compatible = "syscon"; >> + reg = <0x00004078 0x4>; >> + }; >> + >> + pcie3_ctrl: pcie-ctrl@407c { >> + compatible = "syscon"; >> + reg = <0x0000407c 0x4>; >> + }; >> + >> serdes_ln_ctrl: serdes-ln-ctrl@4080 { >> compatible = "mmio-mux"; >> reg = <0x00004080 0x50>; >> @@ -576,6 +596,204 @@ >> }; >> }; >> >> + pcie0_rc: pcie@2900000 { >> + compatible = "ti,j721e-pcie-host"; >> + reg = <0x00 0x02900000 0x00 0x1000>, >> + <0x00 0x02907000 0x00 0x400>, >> + <0x00 0x0d000000 0x00 0x00800000>, >> + <0x00 0x10000000 0x00 0x00001000>; >> + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; >> + interrupt-names = "link_state"; >> + interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; >> + device_type = "pci"; >> + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; >> + max-link-speed = <3>; >> + num-lanes = <2>; >> + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; >> + clocks = <&k3_clks 239 1>; >> + clock-names = "fck"; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + bus-range = <0x0 0xf>; >> + vendor-id = <0x104c>; >> + device-id = <0xb00d>; >> + msi-map = <0x0 &gic_its 0x0 0x10000>; >> + dma-coherent; >> + ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, >> + <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; >> + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; >> + }; >> + >> + pcie0_ep: pcie-ep@2900000 { > Not related to this patch, but just a suggestion: pcie-ep -> do we > need to add that to the Generic names in DT spec? > > [...] >> diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi >> index f787aa73aaae..eeb02115b966 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi >> @@ -132,9 +132,12 @@ >> <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ >> <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ >> <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ >> - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ >> + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ >> + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ >> <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ > ^^ > should be PCIe1? > Just because you are introducing PCIe2,3 in this patch, the net result > does'nt look consistent? Also might want to cover this change in the > $commit_message. yeah, we could have a separate patch for this change. Thanks Kishon > [...] >> <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ >> + <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ >> + <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ >> <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ >> <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ >> <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ >> -- >> 2.17.1 >> >
Hi Rob, On 02/09/20 10:24 am, Kishon Vijay Abraham I wrote: > Hi Nishanth, > > On 01/09/20 8:22 pm, Nishanth Menon wrote: >> On 19:36-20200901, Kishon Vijay Abraham I wrote: >>> Add PCIe device tree node (both RC and EP) for the four >>> PCIe instances here. >>> >>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >>> --- >>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 ++++++++++++++++++++++ >>> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- >>> 2 files changed, 222 insertions(+), 1 deletion(-) >> >> >> Did you look at the diff of the dtbs_check before and after this >> series? I see: https://pastebin.ubuntu.com/p/9fyfrTjx9M/ > > I didn't see any errors when I checked for individual bindings > a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check > DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml" > > SCHEMA Documentation/devicetree/bindings/processed-schema.yaml > DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml > DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml > CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml > CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml > a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check > DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml" > > SCHEMA Documentation/devicetree/bindings/processed-schema.yaml > DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml > DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml > CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml > CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml Can you give hint on why I get ranges is too long error https://pastebin.ubuntu.com/p/cPm2tg3dcV/ which I give mkconfig64 dtbs_check but don't see an error when I include "DT_SCHEMA_FILES"? Thanks Kishon >> >>> >>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >>> b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >>> index 00a36a14efe7..a36909d8b8c3 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >>> @@ -28,6 +28,26 @@ >>> #size-cells = <1>; >>> ranges = <0x0 0x0 0x00100000 0x1c000>; >>> + pcie0_ctrl: pcie-ctrl@4070 { >> https://github.com/devicetree-org/devicetree-specification/releases/download/v0.3/devicetree-specification-v0.3.pdf >> >> Section 2.2.2: why not use syscon@4070 and so on? > > okay, will change to generic name. >> >>> + compatible = "syscon"; >>> + reg = <0x00004070 0x4>; >>> + }; >>> + >>> + pcie1_ctrl: pcie-ctrl@4074 { >>> + compatible = "syscon"; >>> + reg = <0x00004074 0x4>; >>> + }; >>> + >>> + pcie2_ctrl: pcie-ctrl@4078 { >>> + compatible = "syscon"; >>> + reg = <0x00004078 0x4>; >>> + }; >>> + >>> + pcie3_ctrl: pcie-ctrl@407c { >>> + compatible = "syscon"; >>> + reg = <0x0000407c 0x4>; >>> + }; >>> + >>> serdes_ln_ctrl: serdes-ln-ctrl@4080 { >>> compatible = "mmio-mux"; >>> reg = <0x00004080 0x50>; >>> @@ -576,6 +596,204 @@ >>> }; >>> }; >>> + pcie0_rc: pcie@2900000 { >>> + compatible = "ti,j721e-pcie-host"; >>> + reg = <0x00 0x02900000 0x00 0x1000>, >>> + <0x00 0x02907000 0x00 0x400>, >>> + <0x00 0x0d000000 0x00 0x00800000>, >>> + <0x00 0x10000000 0x00 0x00001000>; >>> + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; >>> + interrupt-names = "link_state"; >>> + interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; >>> + device_type = "pci"; >>> + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; >>> + max-link-speed = <3>; >>> + num-lanes = <2>; >>> + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; >>> + clocks = <&k3_clks 239 1>; >>> + clock-names = "fck"; >>> + #address-cells = <3>; >>> + #size-cells = <2>; >>> + bus-range = <0x0 0xf>; >>> + vendor-id = <0x104c>; >>> + device-id = <0xb00d>; >>> + msi-map = <0x0 &gic_its 0x0 0x10000>; >>> + dma-coherent; >>> + ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 >>> 0x0010000>, >>> + <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; >>> + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; >>> + }; >>> + >>> + pcie0_ep: pcie-ep@2900000 { >> Not related to this patch, but just a suggestion: pcie-ep -> do we >> need to add that to the Generic names in DT spec? >> >> [...] >>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi >>> b/arch/arm64/boot/dts/ti/k3-j721e.dtsi >>> index f787aa73aaae..eeb02115b966 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi >>> +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi >>> @@ -132,9 +132,12 @@ >>> <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* >>> USBSS1 */ >>> <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* >>> Most peripherals */ >>> <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* >>> MAIN NAVSS */ >>> - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* >>> PCIe Core*/ >>> + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* >>> PCIe Core*/ >>> + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* >>> PCIe Core*/ >>> <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* >>> PCIe DAT */ >> ^^ >> should be PCIe1? >> Just because you are introducing PCIe2,3 in this patch, the net result >> does'nt look consistent? Also might want to cover this change in the >> $commit_message. > > yeah, we could have a separate patch for this change. > > Thanks > Kishon > >> [...] >>> <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* >>> C71 */ >>> + <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* >>> PCIe2 DAT */ >>> + <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* >>> PCIe3 DAT */ >>> <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* >>> C66_0 */ >>> <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* >>> C66_1 */ >>> <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* >>> GPU */ >>> -- >>> 2.17.1 >>> >>
Hi Rob, On 02/09/20 1:07 pm, Kishon Vijay Abraham I wrote: > Hi Rob, > > On 02/09/20 10:24 am, Kishon Vijay Abraham I wrote: >> Hi Nishanth, >> >> On 01/09/20 8:22 pm, Nishanth Menon wrote: >>> On 19:36-20200901, Kishon Vijay Abraham I wrote: >>>> Add PCIe device tree node (both RC and EP) for the four >>>> PCIe instances here. >>>> >>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >>>> --- >>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 >>>> ++++++++++++++++++++++ >>>> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- >>>> 2 files changed, 222 insertions(+), 1 deletion(-) >>> >>> >>> Did you look at the diff of the dtbs_check before and after this >>> series? I see: https://pastebin.ubuntu.com/p/9fyfrTjx9M/ >> >> I didn't see any errors when I checked for individual bindings >> a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check >> DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml" >> >> SCHEMA Documentation/devicetree/bindings/processed-schema.yaml >> DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml >> DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml >> CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml >> CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml >> a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check >> DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml" >> >> SCHEMA Documentation/devicetree/bindings/processed-schema.yamlsimple-bus >> DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml >> DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml >> CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml >> CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml > > Can you give hint on why I get ranges is too long error > https://pastebin.ubuntu.com/p/cPm2tg3dcV/ which I give mkconfig64 > dtbs_check but don't see an error when I include "DT_SCHEMA_FILES"? I debugged this and looks like PCIe "ranges" property conflicts with simple-bus. A diff like below helps to solve the issue diff --git a/schemas/simple-bus.yaml b/schemas/simple-bus.yaml index 248ac9d..ed818ef 100644 --- a/schemas/simple-bus.yaml +++ b/schemas/simple-bus.yaml @@ -39,7 +39,7 @@ patternProperties: oneOf: - items: minItems: 3 - maxItems: 6 + maxItems: 7 minItems: 0 maxItems: 1024 - $ref: "types.yaml#/definitions/flag" If this looks right to you, I can post a patch for it. Without fixing this we would see false errors for PCIe DT nodes. Thanks Kishon
On 16:53-20200914, Kishon Vijay Abraham I wrote: > Hi Rob, > > On 02/09/20 1:07 pm, Kishon Vijay Abraham I wrote: > > Hi Rob, > > > > On 02/09/20 10:24 am, Kishon Vijay Abraham I wrote: > >> Hi Nishanth, > >> > >> On 01/09/20 8:22 pm, Nishanth Menon wrote: > >>> On 19:36-20200901, Kishon Vijay Abraham I wrote: > >>>> Add PCIe device tree node (both RC and EP) for the four > >>>> PCIe instances here. > >>>> > >>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > >>>> --- > >>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 > >>>> ++++++++++++++++++++++ > >>>> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- > >>>> 2 files changed, 222 insertions(+), 1 deletion(-) > >>> > >>> > >>> Did you look at the diff of the dtbs_check before and after this > >>> series? I see: https://pastebin.ubuntu.com/p/9fyfrTjx9M/ > >> > >> I didn't see any errors when I checked for individual bindings > >> a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check > >> DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml" > >> > >> SCHEMA Documentation/devicetree/bindings/processed-schema.yaml > >> DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml > >> DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml > >> CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml > >> CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml > >> a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check > >> DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml" > >> > >> SCHEMA Documentation/devicetree/bindings/processed-schema.yamlsimple-bus > >> DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml > >> DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml > >> CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml > >> CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml > > > > Can you give hint on why I get ranges is too long error > > https://pastebin.ubuntu.com/p/cPm2tg3dcV/ which I give mkconfig64 > > dtbs_check but don't see an error when I include "DT_SCHEMA_FILES"? > > I debugged this and looks like PCIe "ranges" property conflicts with > simple-bus. > > A diff like below helps to solve the issue > diff --git a/schemas/simple-bus.yaml b/schemas/simple-bus.yaml > index 248ac9d..ed818ef 100644 > --- a/schemas/simple-bus.yaml > +++ b/schemas/simple-bus.yaml > @@ -39,7 +39,7 @@ patternProperties: > oneOf: > - items: > minItems: 3 > - maxItems: 6 > + maxItems: 7 > minItems: 0 > maxItems: 1024 > - $ref: "types.yaml#/definitions/flag" > > If this looks right to you, I can post a patch for it. Without fixing > this we would see false errors for PCIe DT nodes. https://github.com/devicetree-org/dt-schema/commit/3baf308b01786788e3ccb9824fce6d7136b21214 Part of v2020.08.1? Am i missing something?
Hi Nishanth, On 14/09/20 5:22 pm, Nishanth Menon wrote: > On 16:53-20200914, Kishon Vijay Abraham I wrote: >> Hi Rob, >> >> On 02/09/20 1:07 pm, Kishon Vijay Abraham I wrote: >>> Hi Rob, >>> >>> On 02/09/20 10:24 am, Kishon Vijay Abraham I wrote: >>>> Hi Nishanth, >>>> >>>> On 01/09/20 8:22 pm, Nishanth Menon wrote: >>>>> On 19:36-20200901, Kishon Vijay Abraham I wrote: >>>>>> Add PCIe device tree node (both RC and EP) for the four >>>>>> PCIe instances here. >>>>>> >>>>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >>>>>> --- >>>>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 >>>>>> ++++++++++++++++++++++ >>>>>> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- >>>>>> 2 files changed, 222 insertions(+), 1 deletion(-) >>>>> >>>>> >>>>> Did you look at the diff of the dtbs_check before and after this >>>>> series? I see: https://pastebin.ubuntu.com/p/9fyfrTjx9M/ >>>> >>>> I didn't see any errors when I checked for individual bindings >>>> a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check >>>> DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml" >>>> >>>> SCHEMA Documentation/devicetree/bindings/processed-schema.yaml >>>> DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml >>>> DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml >>>> CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml >>>> CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml >>>> a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check >>>> DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml" >>>> >>>> SCHEMA Documentation/devicetree/bindings/processed-schema.yamlsimple-bus >>>> DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml >>>> DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml >>>> CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml >>>> CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml >>> >>> Can you give hint on why I get ranges is too long error >>> https://pastebin.ubuntu.com/p/cPm2tg3dcV/ which I give mkconfig64 >>> dtbs_check but don't see an error when I include "DT_SCHEMA_FILES"? >> >> I debugged this and looks like PCIe "ranges" property conflicts with >> simple-bus. >> >> A diff like below helps to solve the issue >> diff --git a/schemas/simple-bus.yaml b/schemas/simple-bus.yaml >> index 248ac9d..ed818ef 100644 >> --- a/schemas/simple-bus.yaml >> +++ b/schemas/simple-bus.yaml >> @@ -39,7 +39,7 @@ patternProperties: >> oneOf: >> - items: >> minItems: 3 >> - maxItems: 6 >> + maxItems: 7 >> minItems: 0 >> maxItems: 1024 >> - $ref: "types.yaml#/definitions/flag" >> >> If this looks right to you, I can post a patch for it. Without fixing >> this we would see false errors for PCIe DT nodes. > > https://github.com/devicetree-org/dt-schema/commit/3baf308b01786788e3ccb9824fce6d7136b21214 > > Part of v2020.08.1? Am i missing something? I think I was using a different repo https://github.com/robherring/dt-schema.git. Do you see the following issues you reported earlier with v2020.08.1? +/home/nmenon/Src/opensource/linux/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml: bus@100000: pcie@2900000:ranges: [[16777216, 0, 268439552, 0, 268439552, 0, 65536], [33554432, 0, 268505088, 0, 268505088, 0, 134148096]] is not valid under any of the given schemas (Possible causes of the failure): + /home/nmenon/Src/opensource/linux/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml: bus@100000: pcie@2900000:ranges: True was expected + /home/nmenon/Src/opensource/linux/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml: bus@100000: pcie@2900000:ranges:0: [16777216, 0, 268439552, 0, 268439552, 0, 65536] is too long + /home/nmenon/Src/opensource/linux/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml: bus@100000: pcie@2900000:ranges:1: [33554432, 0, 268505088, 0, 268505088, 0, 134148096] is too long + Thanks Kishon >
On 17:43-20200914, Kishon Vijay Abraham I wrote: > Hi Nishanth, > > On 14/09/20 5:22 pm, Nishanth Menon wrote: > > On 16:53-20200914, Kishon Vijay Abraham I wrote: > >> Hi Rob, > >> > >> On 02/09/20 1:07 pm, Kishon Vijay Abraham I wrote: > >>> Hi Rob, > >>> > >>> On 02/09/20 10:24 am, Kishon Vijay Abraham I wrote: > >>>> Hi Nishanth, > >>>> > >>>> On 01/09/20 8:22 pm, Nishanth Menon wrote: > >>>>> On 19:36-20200901, Kishon Vijay Abraham I wrote: > >>>>>> Add PCIe device tree node (both RC and EP) for the four > >>>>>> PCIe instances here. > >>>>>> > >>>>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > >>>>>> --- > >>>>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 > >>>>>> ++++++++++++++++++++++ > >>>>>> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- > >>>>>> 2 files changed, 222 insertions(+), 1 deletion(-) > >>>>> > >>>>> > >>>>> Did you look at the diff of the dtbs_check before and after this > >>>>> series? I see: https://pastebin.ubuntu.com/p/9fyfrTjx9M/ > >>>> > >>>> I didn't see any errors when I checked for individual bindings > >>>> a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check > >>>> DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml" > >>>> > >>>> SCHEMA Documentation/devicetree/bindings/processed-schema.yaml > >>>> DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml > >>>> DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml > >>>> CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml > >>>> CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml > >>>> a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check > >>>> DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml" > >>>> > >>>> SCHEMA Documentation/devicetree/bindings/processed-schema.yamlsimple-bus > >>>> DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml > >>>> DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml > >>>> CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml > >>>> CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml > >>> > >>> Can you give hint on why I get ranges is too long error > >>> https://pastebin.ubuntu.com/p/cPm2tg3dcV/ which I give mkconfig64 > >>> dtbs_check but don't see an error when I include "DT_SCHEMA_FILES"? > >> > >> I debugged this and looks like PCIe "ranges" property conflicts with > >> simple-bus. > >> > >> A diff like below helps to solve the issue > >> diff --git a/schemas/simple-bus.yaml b/schemas/simple-bus.yaml > >> index 248ac9d..ed818ef 100644 > >> --- a/schemas/simple-bus.yaml > >> +++ b/schemas/simple-bus.yaml > >> @@ -39,7 +39,7 @@ patternProperties: > >> oneOf: > >> - items: > >> minItems: 3 > >> - maxItems: 6 > >> + maxItems: 7 > >> minItems: 0 > >> maxItems: 1024 > >> - $ref: "types.yaml#/definitions/flag" > >> > >> If this looks right to you, I can post a patch for it. Without fixing > >> this we would see false errors for PCIe DT nodes. > > > > https://github.com/devicetree-org/dt-schema/commit/3baf308b01786788e3ccb9824fce6d7136b21214 > > > > Part of v2020.08.1? Am i missing something? > > I think I was using a different repo > https://github.com/robherring/dt-schema.git. > > Do you see the following issues you reported earlier with v2020.08.1? > > +/home/nmenon/Src/opensource/linux/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml: > bus@100000: pcie@2900000:ranges: [[16777216, 0, 268439552, 0, 268439552, > 0, 65536], [33554432, 0, 268505088, 0, 268505088, 0, 134148096]] is not > valid under any of the given schemas (Possible causes of the failure): > + > /home/nmenon/Src/opensource/linux/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml: > bus@100000: pcie@2900000:ranges: True was expected > + > /home/nmenon/Src/opensource/linux/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml: > bus@100000: pcie@2900000:ranges:0: [16777216, 0, 268439552, 0, > 268439552, 0, 65536] is too long > + > /home/nmenon/Src/opensource/linux/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml: > bus@100000: pcie@2900000:ranges:1: [33554432, 0, 268505088, 0, > 268505088, 0, 134148096] is too long Arrgh.. you are right.. Looks like one of my PCs still had 2020.8 instead of 2020.8.1. We just need to figure out what is going on with syscon.yaml as against ti,j721e-system-controller.yaml..
Hi Nishanth, On 14/09/20 6:44 pm, Nishanth Menon wrote: > On 17:43-20200914, Kishon Vijay Abraham I wrote: >> Hi Nishanth, >> >> On 14/09/20 5:22 pm, Nishanth Menon wrote: >>> On 16:53-20200914, Kishon Vijay Abraham I wrote: >>>> Hi Rob, >>>> >>>> On 02/09/20 1:07 pm, Kishon Vijay Abraham I wrote: >>>>> Hi Rob, >>>>> >>>>> On 02/09/20 10:24 am, Kishon Vijay Abraham I wrote: >>>>>> Hi Nishanth, >>>>>> >>>>>> On 01/09/20 8:22 pm, Nishanth Menon wrote: >>>>>>> On 19:36-20200901, Kishon Vijay Abraham I wrote: >>>>>>>> Add PCIe device tree node (both RC and EP) for the four >>>>>>>> PCIe instances here. >>>>>>>> >>>>>>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >>>>>>>> --- >>>>>>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 >>>>>>>> ++++++++++++++++++++++ >>>>>>>> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- >>>>>>>> 2 files changed, 222 insertions(+), 1 deletion(-) >>>>>>> >>>>>>> >>>>>>> Did you look at the diff of the dtbs_check before and after this >>>>>>> series? I see: https://pastebin.ubuntu.com/p/9fyfrTjx9M/ >>>>>> >>>>>> I didn't see any errors when I checked for individual bindings >>>>>> a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check >>>>>> DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml" >>>>>> >>>>>> SCHEMA Documentation/devicetree/bindings/processed-schema.yaml >>>>>> DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml >>>>>> DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml >>>>>> CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml >>>>>> CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml >>>>>> a0393678@a0393678-ssd:~/repos/linux$ mkconfig64 dtbs_check >>>>>> DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml" >>>>>> >>>>>> SCHEMA Documentation/devicetree/bindings/processed-schema.yamlsimple-bus >>>>>> DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml >>>>>> DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml >>>>>> CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml >>>>>> CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml >>>>> >>>>> Can you give hint on why I get ranges is too long error >>>>> https://pastebin.ubuntu.com/p/cPm2tg3dcV/ which I give mkconfig64 >>>>> dtbs_check but don't see an error when I include "DT_SCHEMA_FILES"? >>>> >>>> I debugged this and looks like PCIe "ranges" property conflicts with >>>> simple-bus. >>>> >>>> A diff like below helps to solve the issue >>>> diff --git a/schemas/simple-bus.yaml b/schemas/simple-bus.yaml >>>> index 248ac9d..ed818ef 100644 >>>> --- a/schemas/simple-bus.yaml >>>> +++ b/schemas/simple-bus.yaml >>>> @@ -39,7 +39,7 @@ patternProperties: >>>> oneOf: >>>> - items: >>>> minItems: 3 >>>> - maxItems: 6 >>>> + maxItems: 7 >>>> minItems: 0 >>>> maxItems: 1024 >>>> - $ref: "types.yaml#/definitions/flag" >>>> >>>> If this looks right to you, I can post a patch for it. Without fixing >>>> this we would see false errors for PCIe DT nodes. >>> >>> https://github.com/devicetree-org/dt-schema/commit/3baf308b01786788e3ccb9824fce6d7136b21214 >>> >>> Part of v2020.08.1? Am i missing something? >> >> I think I was using a different repo >> https://github.com/robherring/dt-schema.git. >> >> Do you see the following issues you reported earlier with v2020.08.1? >> >> +/home/nmenon/Src/opensource/linux/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml: >> bus@100000: pcie@2900000:ranges: [[16777216, 0, 268439552, 0, 268439552, >> 0, 65536], [33554432, 0, 268505088, 0, 268505088, 0, 134148096]] is not >> valid under any of the given schemas (Possible causes of the failure): >> + >> /home/nmenon/Src/opensource/linux/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml: >> bus@100000: pcie@2900000:ranges: True was expected >> + >> /home/nmenon/Src/opensource/linux/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml: >> bus@100000: pcie@2900000:ranges:0: [16777216, 0, 268439552, 0, >> 268439552, 0, 65536] is too long >> + >> /home/nmenon/Src/opensource/linux/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml: >> bus@100000: pcie@2900000:ranges:1: [33554432, 0, 268505088, 0, >> 268505088, 0, 134148096] is too long > > > Arrgh.. you are right.. Looks like one of my PCs still had 2020.8 > instead of 2020.8.1. We just need to figure out what is going on with > syscon.yaml as against ti,j721e-system-controller.yaml.. I think I'll use the existing TI specific compatible string for syscon here. Thanks Kishon
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 00a36a14efe7..a36909d8b8c3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -28,6 +28,26 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; + pcie0_ctrl: pcie-ctrl@4070 { + compatible = "syscon"; + reg = <0x00004070 0x4>; + }; + + pcie1_ctrl: pcie-ctrl@4074 { + compatible = "syscon"; + reg = <0x00004074 0x4>; + }; + + pcie2_ctrl: pcie-ctrl@4078 { + compatible = "syscon"; + reg = <0x00004078 0x4>; + }; + + pcie3_ctrl: pcie-ctrl@407c { + compatible = "syscon"; + reg = <0x0000407c 0x4>; + }; + serdes_ln_ctrl: serdes-ln-ctrl@4080 { compatible = "mmio-mux"; reg = <0x00004080 0x50>; @@ -576,6 +596,204 @@ }; }; + pcie0_rc: pcie@2900000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie0_ep: pcie-ep@2900000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + }; + + pcie1_rc: pcie@2910000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x10000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + }; + + pcie2_rc: pcie@2920000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02920000 0x00 0x1000>, + <0x00 0x02927000 0x00 0x400>, + <0x00 0x0e000000 0x00 0x00800000>, + <0x44 0x00000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 241 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x20000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, + <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie2_ep: pcie-ep@2920000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02920000 0x00 0x1000>, + <0x00 0x02927000 0x00 0x400>, + <0x00 0x0e000000 0x00 0x00800000>, + <0x44 0x00000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 241 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + }; + + pcie3_rc: pcie@2930000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02930000 0x00 0x1000>, + <0x00 0x02937000 0x00 0x400>, + <0x00 0x0e800000 0x00 0x00800000>, + <0x44 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 242 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x30000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie3_ep: pcie-ep@2930000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02930000 0x00 0x1000>, + <0x00 0x02937000 0x00 0x400>, + <0x00 0x0e800000 0x00 0x00800000>, + <0x44 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 242 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + #address-cells = <2>; + #size-cells = <2>; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index f787aa73aaae..eeb02115b966 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -132,9 +132,12 @@ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ + <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ + <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
Add PCIe device tree node (both RC and EP) for the four PCIe instances here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 ++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- 2 files changed, 222 insertions(+), 1 deletion(-)