| Message ID | 20200923005858.148261-2-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show
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a=rsa-sha256; c=simple/simple; d=aosc.io; s=default; t=1600822752; bh=kPoz5xWCZ0urom+8cz1Y5v7QCbvCnYjIYd/MWXLbPPA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fiemhAgr4eeksuPhmwyjvUsbjIZsRc3MHKzpNOhgW5EMKktyflRVtHhg4fWDFRYvo XtrEeP/edMzZxV+ydde+jWX4k6oFeWMqzuRhHp3+Ezx25dJ+nNzAD93eIelWe4HN9G 6IA1ycDu83GGRuf14o/+wCiK66BZgAbQjviPtyHU= From: Icenowy Zheng <icenowy@aosc.io> To: Rob Herring <robh+dt@kernel.org>, Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org> Subject: [PATCH 3/7] ARM: dts: sun8i: V3/V3s/S3/S3L: add CSI1 device node Date: Wed, 23 Sep 2020 08:58:54 +0800 Message-Id: <20200923005858.148261-2-icenowy@aosc.io> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200923005858.148261-1-icenowy@aosc.io> References: <20200923005709.147966-1-icenowy@aosc.io> <20200923005858.148261-1-icenowy@aosc.io> MIME-Version: 1.0 X-Rspamd-Queue-Id: A1C7B41009 X-Spamd-Result: default: False [6.40 / 20.00]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; R_DKIM_ALLOW(0.00)[aosc.io:s=default]; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org |
| Series |
Pine64 PineCube support
|
expand
|
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 4cfdf193cf88..3e079973672d 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -488,6 +488,18 @@ spi0: spi@1c68000 { #size-cells = <0>; }; + csi1: camera@1cb4000 { + compatible = "allwinner,sun8i-v3s-csi"; + reg = <0x01cb4000 0x3000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>,
The CSI1 controller of V3/V3s/S3/S3L chips is used for parallel CSI. Add the device tree node of it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)