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Tue, 29 Sep 2020 05:46:54 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 29 Sep 2020 06:46:52 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 29 Sep 2020 21:46:50 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 29 Sep 2020 21:46:49 +0800 From: Crystal Guo To: , , Subject: [v5,1/3] dt-binding: reset-controller: mediatek: add YAML schemas Date: Tue, 29 Sep 2020 21:46:40 +0800 Message-ID: <20200929134642.26561-2-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200929134642.26561-1-crystal.guo@mediatek.com> References: <20200929134642.26561-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200929_094708_078120_583BE1E1 X-CRM114-Status: GOOD ( 13.09 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, yong.liang@mediatek.com, stanley.chu@mediatek.com, srv_heupstream@mediatek.com, seiya.wang@mediatek.com, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, Crystal Guo , linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add a YAML documentation for Mediatek, which uses ti reset-controller driver directly. The TI reset controller provides a common reset management, and is suitable for Mediatek SoCs. Signed-off-by: Crystal Guo --- .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml new file mode 100644 index 000000000000..dab630e95a0d --- /dev/null +++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Reset Controller + +maintainers: + - Crystal Guo + +description: + The bindings describe the reset-controller for Mediatek SoCs, + which is based on TI reset controller. For more detail, please + visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. + +properties: + compatible: + const: mediatek,syscon-reset + + '#reset-cells': + const: 1 + + mediatek,reset-bits: + description: > + Contains the reset control register information, please refer to + Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. + +required: + - compatible + - '#reset-cells' + - mediatek,reset-bits + +additionalProperties: false + +examples: + - | + #include + infracfg: infracfg@10001000 { + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + + infracfg_rst: reset-controller { + compatible = "mediatek,syscon-reset"; + #reset-cells = <1>; + mediatek,reset-bits = < + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + >; + }; + };