| Message ID | 20200930020710.7394-5-yifeng.zhao@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Rockchip NFC drivers for RK3308 and others | expand |
On 2020/9/30 上午10:07, Yifeng Zhao wrote: > From: Yifeng Zhao <zyf@rock-chips.com> > > Add NAND FLASH Controller(NFC) node for RK3308 SoC. > > Signed-off-by: Yifeng Zhao <zyf@rock-chips.com> > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> > --- > > Changes in v10: None > Changes in v9: None > Changes in v8: None > Changes in v7: None > Changes in v6: None > Changes in v5: None > Changes in v4: None > Changes in v3: None > Changes in v2: None > > arch/arm64/boot/dts/rockchip/rk3308.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) Looks good to me, Reviewed-by: Kever Yang<kever.yang@rock-chips.com> Thanks, - Kever > > diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi > index 0cf954062387..f98c65c9bd13 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi > @@ -629,6 +629,21 @@ > status = "disabled"; > }; > > + nfc: nand-controller@ff4b0000 { > + compatible = "rockchip,rk3308-nfc", > + "rockchip,rv1108-nfc"; > + reg = <0x0 0xff4b0000 0x0 0x4000>; > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; > + clock-names = "ahb", "nfc"; > + assigned-clocks = <&cru SCLK_NANDC>; > + assigned-clock-rates = <150000000>; > + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 > + &flash_rdn &flash_rdy &flash_wrn>; > + pinctrl-names = "default"; > + status = "disabled"; > + }; > + > cru: clock-controller@ff500000 { > compatible = "rockchip,rk3308-cru"; > reg = <0x0 0xff500000 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 0cf954062387..f98c65c9bd13 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -629,6 +629,21 @@ status = "disabled"; }; + nfc: nand-controller@ff4b0000 { + compatible = "rockchip,rk3308-nfc", + "rockchip,rv1108-nfc"; + reg = <0x0 0xff4b0000 0x0 0x4000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; + clock-names = "ahb", "nfc"; + assigned-clocks = <&cru SCLK_NANDC>; + assigned-clock-rates = <150000000>; + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 + &flash_rdn &flash_rdy &flash_wrn>; + pinctrl-names = "default"; + status = "disabled"; + }; + cru: clock-controller@ff500000 { compatible = "rockchip,rk3308-cru"; reg = <0x0 0xff500000 0x0 0x1000>;