From patchwork Thu Oct 1 16:01:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 11811783 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 39EB46CA for ; Thu, 1 Oct 2020 16:03:10 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0E95F208B6 for ; Thu, 1 Oct 2020 16:03:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="x+OLBqzA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0E95F208B6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=collabora.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BnJUVWcIWq9FcLrBZhCUzEHwaOBpDZa8imuqqrHp+mY=; b=x+OLBqzAEhLekDu3+0hP+RSWH w3jfQ1m2DuR9dsCG/aLlHC+kLbwcPMy+Cr9YzXndS4tboO5W/hYdNHY1B61/0giDjKaGXKA64vdeK q0PBIqLNSyAUSUx3aCkec24hl6b+DhGMv0UlTZPmC5bFB0fjDS749ScuiF/6geCKIgltwBSaShNc7 AVDUlyXQ+SsakdWz5QLxsrenXXFFoSGa2ABDacKpa6w0c05dQw0bCDPYOiao70p4mgGcbnsRF6FJ+ 6BAXG+JgTWH+ejV+MfSwUIKY6+ZBxexfz0N5UR+KBMehHtNuuuI+zvfqgnmoJi0o+APOoh3XVJTnZ 76DD1siXg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kO12j-0000Mv-2P; Thu, 01 Oct 2020 16:02:53 +0000 Received: from bhuna.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e3e3]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kO122-0008PV-Fi; Thu, 01 Oct 2020 16:02:11 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id A015929D759 From: Enric Balletbo i Serra To: linux-kernel@vger.kernel.org Subject: [PATCH v2 07/12] soc: mediatek: pm-domains: Add extra sram control Date: Thu, 1 Oct 2020 18:01:49 +0200 Message-Id: <20201001160154.3587848-8-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201001160154.3587848-1-enric.balletbo@collabora.com> References: <20201001160154.3587848-1-enric.balletbo@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201001_120210_644587_91551ABD X-CRM114-Status: GOOD ( 13.58 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drinkcat@chromium.org, weiyi.lu@mediatek.com, fparent@baylibre.com, Matthias Brugger , linux-mediatek@lists.infradead.org, hsinyi@chromium.org, matthias.bgg@gmail.com, Collabora Kernel ML , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Matthias Brugger For some power domains like vpu_core on MT8183 whose sram need to do clock and internal isolation while power on/off sram. We add a cap "MTK_SCPD_SRAM_ISO" to judge if we need to do the extra sram isolation control or not. Signed-off-by: Weiyi Lu Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra --- Changes in v2: - Nit, split readl(ctl_addr) | pd->data->sram_pdn_bits in two lines. - Use regmap API drivers/soc/mediatek/mtk-pm-domains.c | 30 +++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 38f2630bdd0a..e0a52d489fea 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -21,6 +21,7 @@ #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) +#define MTK_SCPD_SRAM_ISO BIT(2) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 @@ -42,6 +43,8 @@ #define PWR_ON_BIT BIT(2) #define PWR_ON_2ND_BIT BIT(3) #define PWR_CLK_DIS_BIT BIT(4) +#define PWR_SRAM_CLKISO_BIT BIT(5) +#define PWR_SRAM_ISOINT_B_BIT BIT(6) #define PWR_STATUS_DISP BIT(3) #define PWR_STATUS_MFG BIT(4) @@ -155,14 +158,28 @@ static int scpsys_sram_enable(struct scpsys_domain *pd) struct scpsys *scpsys = pd->scpsys; u32 val; int tmp; + int ret; regmap_read(scpsys->base, pd->data->ctl_offs, &val); val &= ~pd->data->sram_pdn_bits; regmap_write(scpsys->base, pd->data->ctl_offs, val); /* Either wait until SRAM_PDN_ACK all 1 or 0 */ - return regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, - (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret = regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, + (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + if (ret < 0) + return ret; + + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) { + regmap_read(scpsys->base, pd->data->ctl_offs, &val); + val |= PWR_SRAM_ISOINT_B_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + udelay(1); + val &= ~PWR_SRAM_CLKISO_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + } + + return 0; } static int scpsys_sram_disable(struct scpsys_domain *pd) @@ -172,6 +189,15 @@ static int scpsys_sram_disable(struct scpsys_domain *pd) u32 val; int tmp; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) { + regmap_read(scpsys->base, pd->data->ctl_offs, &val); + val |= PWR_SRAM_CLKISO_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + val &= ~PWR_SRAM_ISOINT_B_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + udelay(1); + } + regmap_read(scpsys->base, pd->data->ctl_offs, &val); val |= pd->data->sram_pdn_bits; regmap_write(scpsys->base, pd->data->ctl_offs, val);