| Message ID | 20201006200316.2261245-2-lars.povlsen@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | power: Add reset support for Microchip Sparx5 SoC | expand |
On Tue, 06 Oct 2020 22:03:14 +0200, Lars Povlsen wrote: > This adds the support for the Sparx5 SoC. > > Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> > --- > .../devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++-- > MAINTAINERS | 1 + > 2 files changed, 6 insertions(+), 2 deletions(-) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt index 1b4213eb3473..4d530d815484 100644 --- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -1,10 +1,13 @@ Microsemi Ocelot reset controller The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the -SoC MIPS core. +SoC core. + +The reset registers are both present in the MSCC vcoreiii MIPS and +microchip Sparx5 armv8 SoC's. Required Properties: - - compatible: "mscc,ocelot-chip-reset" + - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset" Example: reset@1070008 { diff --git a/MAINTAINERS b/MAINTAINERS index deaafb617361..cc70e3ab428b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11516,6 +11516,7 @@ M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com> L: linux-mips@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/mips/mscc.txt +F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt F: arch/mips/boot/dts/mscc/ F: arch/mips/configs/generic/board-ocelot.config F: arch/mips/generic/board-ocelot.c
This adds the support for the Sparx5 SoC. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> --- .../devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++-- MAINTAINERS | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) -- 2.25.1