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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kRGrO-0005Um-3P; Sat, 10 Oct 2020 15:32:38 +0000 Received: from o1.b.az.sendgrid.net ([208.117.55.133]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kRGr6-0005Pf-8K for linux-arm-kernel@lists.infradead.org; Sat, 10 Oct 2020 15:32:23 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=from:subject:in-reply-to:references:to:cc:content-type: content-transfer-encoding; s=001; bh=nAJZakghzr7JwdXt31dydBHC6AGXJnAIYTAyCKaQf5U=; b=PC35notrsluMKEtXrx+00hA/7mdLEP0dYlDe5YZ4F97AxB2FbB1c+8wCFl2DT/ypo8SJ lktfdkzCJKjCzl6ik8zAmz7ahPHYTYZbHZAUJ/VCbQDdzWzpDWDvovYpuhFxqqZFIH7ARr liinpjGwGy/EmEckcg2tKrDKhnMhEQcwo= Received: by filterdrecv-p3mdw1-6685f47d68-ckbbx with SMTP id filterdrecv-p3mdw1-6685f47d68-ckbbx-20-5F81D403-62 2020-10-10 15:32:19.989765983 +0000 UTC m=+233779.068193756 Received: from bionic.localdomain (unknown) by ismtpd0005p1lon1.sendgrid.net (SG) with ESMTP id svU4HSZBQumIlycPppIvOg Sat, 10 Oct 2020 15:32:19.702 +0000 (UTC) From: Jonas Karlman Subject: [PATCH v3 5/6] phy/rockchip: inno-hdmi: force set_rate on power_on Date: Sat, 10 Oct 2020 15:32:20 +0000 (UTC) Message-Id: <20201010153214.19722-6-jonas@kwiboo.se> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201010153214.19722-1-jonas@kwiboo.se> References: <20200108210740.28769-1-jonas@kwiboo.se> <20201010153214.19722-1-jonas@kwiboo.se> X-SG-EID: TdbjyGynYnRZWhH+7lKUQJL+ZxmxpowvO2O9SQF5CwCVrYgcwUXgU5DKUU3QxAfZekEeQsTe+RrMu3cja6a0hyyYIFNv1tq5H+1qUNYBOeobs/kbfAS1O/yl8F4W63ETW0ZJQ8LdMpvZXyiq4Ios7vQDZpdGL3Mwe6lFjuXN1jpUjyJ23XE36iemJDYWvFwuG48f3zchrzY6FEAPEmcFpbmiBN+ALFiHjyO3swFoURJRwKh58QiWxd3QkpVOZk/szt6XV24plpsg+U/5CH6N/A== To: Kishon Vijay Abraham I , Heiko Stuebner X-Entity-ID: wSPGWgGSXUap++qShBI+ag== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201010_113220_374685_455A923D X-CRM114-Status: GOOD ( 13.28 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [208.117.55.133 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Algea Cao , Jonas Karlman , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Vinod Koul , Huicong Xu , linux-arm-kernel@lists.infradead.org, Zheng Yang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Huicong Xu Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and not in pixel clock rate. When the hdmiphy clock is configured with the same pixel clock rate using clk_set_rate() the clock framework do not signal the hdmi phy driver to set_rate when switching between 8-bit and Deep Color. This result in pre/post pll not being re-configured when switching between regular 8-bit and Deep Color video formats. Fix this by calling set_rate in power_on to force pre pll re-configuration. Signed-off-by: Huicong Xu Signed-off-by: Jonas Karlman --- drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c index 3a59a6da0440..3719309ad0d0 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -245,6 +245,7 @@ struct inno_hdmi_phy { struct clk_hw hw; struct clk *phyclk; unsigned long pixclock; + unsigned long tmdsclock; }; struct pre_pll_config { @@ -485,6 +486,8 @@ static int inno_hdmi_phy_power_on(struct phy *phy) dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); + inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000); + ret = clk_prepare_enable(inno->phyclk); if (ret) return ret; @@ -509,6 +512,8 @@ static int inno_hdmi_phy_power_off(struct phy *phy) clk_disable_unprepare(inno->phyclk); + inno->tmdsclock = 0; + dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); return 0; @@ -628,6 +633,9 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", __func__, rate, tmdsclock); + if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) + return 0; + cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); if (IS_ERR(cfg)) return PTR_ERR(cfg); @@ -670,6 +678,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, } inno->pixclock = rate; + inno->tmdsclock = tmdsclock; return 0; } @@ -781,6 +790,9 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", __func__, rate, tmdsclock); + if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) + return 0; + cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); if (IS_ERR(cfg)) return PTR_ERR(cfg); @@ -820,6 +832,7 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, } inno->pixclock = rate; + inno->tmdsclock = tmdsclock; return 0; }